Junctionless Transistor Research Articles

A Nanoscale‐Modified band energy junctionless transistor with considerable progress on the electrical and frequency issue

One of the serious prevalent weaknesses for silicon-on-insulator junctionless (CSOI-JLT) devices is high leakage current resulting in the limitation of it in nanoscale circuits. To solve this main concern, an efficient technique relying on the modification of band energy profile has been suggested. To reach this important achievement, a special part of the buried oxide (BOX) is replaced by the silicon material (Si) which is the same as the substrate in terms of type and doping concentration. Dividing the BOX redistributes the band energy and makes the channel region (Ch/R) near the source narrower which is desirable in the off-state situation. The considerable reduction of the leakage current and increase in the current gain (Ion/Ioff) is exhibited in the proposed structure. The modification of band energy for the suggested junctionless is announced as an initial start for improvement of the electrical performance in terms of leakage current, subthreshold swing (SS), global lattice temperature (GLT), electron velocity, output conductance, unilateral power gain, cut-off frequency, maximum oscillation frequency, total gate capacitance and minimum noise figure as compared to the common junctionless (CSOI-JLT).

Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

In this paper, an analytical predictive model of interface charge traps in symmetric long channel double-gate junctionless transistors is proposed based on a charge-based model. Interface charge traps arising from the exposure to chemicals, high-energy ionizing radiation or aging mechanism could degrade the charge-voltage characteristics. The model is predictive in a range of temperature from 77K to 400K. The validity of the approach is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation from deep depletion to accumulation and linear to saturation.

Impact of two gate oxide with no junction metal oxide semiconductor field effect transistor- an analytical model

Abstract An analytical model based on physics is used to describe the potential distribution, horizontal electric field, and drain current of Two Gate Oxide with no junction MOSFET (TOX-NOJ-MOSFET) was investigated for cylindrical shape structure. The Poisson equation is used to derive the expression for cylindrical coordinate system which relies on parabolic approximation method. The combination of high k two gate oxide stack and junctionless transistor with Dual material Double gate structure performs a major role to diminish the short channel effects, propelled to increase the ION current (10−5A/μm) and decrease the leakage current IOFF of 10−14 A/μm to enhance ION/IOFF ratio to 109. To ensure the scalability and responsiveness of the system numerical simulations have been performed with various bias voltages and gate length ratios using Synopsys TCAD software and the results were well matched with analytical solutions.

SEU Performance Enhancement in BPJLT Devices by Channel Doping and Film Thickness

The bulk planar junctionless transistor (BPJLT) is a potential candidate for future CMOS technologies due to its CMOS compatibility and scalability. In this paper, the impact of silicon film thickness and channel doping on single-event upset (SEU) radiation performance of BPJLT based SRAMs is studied using TCAD simulations. The simulation results show that BPJLT devices having higher channel doping and smaller film thickness provides the better SEU performance.

Modeling of dual material surrounding split gate junctionless transistor as biosensor

In this paper an analytical model of dual material surrounding split gate junctionless transistor for application as a biosensor is introduced. The simulation results show fair compatibility with the analytical models developed for the channel center potential and threshold voltage at channel length of 45 nm and 20 nm. For the detection of the bio-molecules, concept of dielectric modulation has been used. The model shows a satisfactory value of sensitivity in the range of 0–0.27 and 0–0.8 for relative permittivity of biomolecules varying from 1 to 9 at channel length of 45 nm and 20 nm respectively, thus making it an attractive option for use as biosensor. This model has been demonstrated with the aid of TCAD device simulations. • Present work includes modelling of dual material surrounding split gate junction less transistor for bio-sensing application. • The model for channel centre potential and threshold voltage has been developed. • Sensitivity is defined in terms of change in threshold voltage of the device. • Decent sensitivity in the range of 0–0.27 and 0–0.8 for 45 nm and 20 nm technology respectively is observed for relative permittivity varying from 1–9.

Bi-Directional Junctionless Transistor for Logic and Memory Applications

This article reports on logic and memory functionality of vertically stacked bidirectional junctionless (BiJL) transistor, which can be operated as nMOS or pMOS depending on the biases applied. An inverter can be realized with a single BiJL transistor. If a complement of inputs is available, then NAND, NOR, and XOR logic can also be realized through a single BiJL transistor. The thickness of separation oxide between n-type and p-type films can be utilized to either achieve hysteresis or the absence of the same. Results provide insights into device physics, operation, and showcase new viewpoints for designing logic and memory devices with vertically stacked JL architecture, thus achieving the desired functionality with a lesser number of transistors.

Upgrade of Drain Current Compact Model for Nanoscale Triple-Gate Junctionless Transistors to Continuous and Symmetric

In this brief, we upgrade our initial drain current compact model for triple-gate junctionless transistors (JLTs) to a continuous model satisfying the source/drain (S/D) symmetry. This is achieved by reformulating the key equations of our original model, using Lambert-function-based terminal charges. The upgraded model is compact, bulk-referenced valid in all regions of operation and it is validated through comparison with experimental data to verify its accuracy. The symmetry condition is investigated and validated performing the dc Gummel symmetry test (GST) for all derivatives up to the fifth order.

Si/Ge Hetero Tunnel Field-Effect Transistor with Junctionless Channel Based on Nanowire.

A Si/Ge hetero tunnel field-effect transistor (TFET) with junctionless channel based on nanowire (JLNW-TFET) is proposed, and its electrical performance and dependency of natural parameters are investigated. The JLNW-TFET is operated by compensating each demerit of the following two mechanisms: thermionic generation of junctionless field-effect transistor (JLFET) and band to band tunneling (BTBT) generation of tunnel field-effect transistor (TFET). Although the on-current Ion of JLNW-TFET decreases approximately ten times as much as that of the conventional TFET, its subthreshold swing SS is three times steeper than that of the conventional TFET and ambipolar current Iambipolar does not appear as a result of the structural characteristics. Ioff increases due to Shockley-Read-Hall (SRH) recombination when the density of traps increases; however, an increase in SS is not observed. At temperatures higher than room temperature, Ioff increases slightly and SS and Ion are almost constant. Furthermore, quantum confinement and trap assisted tunneling do not significantly affect the performance of the devices except for increasing Ioff and slightly decreasing Ion.

Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture

This paper proposes a p-type double gate junctionless field effect transistor having opposite doping in the core with that of the silicon body referring to rectangular core–shell (RCS) architecture. The use of RCS has significantly reduced the gate induced drain leakage and therefore, obtaining improved performance parameters. It is observed that the parasitic BJT action gets diminished in RCS architecture due to enlargement of tunneling width at the channel/drain interface. Further, after validating our simulations with the experimental results of junctionless p-type FET we demonstrated that insertion of oppositely doped core in silicon body helps to achieve volume depletion in OFF state. The simulation results show that junctionless FET with RCS architecture exhibit lower OFF current, higher ON/OFF ratio, better drain induced barrier lowering (DIBL) and superior subthreshold slope (SS) at lesser channel lengths. The measured values of OFF current, ON current, ON/OFF ratio, DIBL and SS at channel length 20 nm for RCS architecture are −9.96 × 10−15 A, −2.33 × 10−5 A, 0.23 × 1010, 42.1 mV V−1 and 67.7 mV/decade respectively. Interestingly, we have found a correlation between RCS thickness and channel length. Finally, a complementary metal oxide semiconductor (CMOS) inverter with RCS architecture is also designed. The voltage transfer characteristics of RCS based CMOS has been significantly improved as compared to the conventional junctionless CMOS inverter.

Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode

Capacitorless DRAM (1T-DRAM) is considered to be a promising candidate to replace conventional 1T-1C DRAM which is facing a scaling limit. 1T-DRAM with a poly-Si body has attracted much attention specifically for its simple SOI fabrication and stackable memory which allow for ultrahigh density. A single crystal silicon-based junctionless (JL) transistor is unsuitable for a 1T-DRAM cell because the transistor’s body is too thin to have a storage region and its junction barrier is too low to store holes. In contrast, a JL transistor with a thin poly-Si body can be used as a 1T-DRAM cell because it uses a grain boundary as its charge storage region instead of a floating body. We carried out intensive simulations of JL transistors with poly-Si body and confirmed the possibility of using a JL structure as a poly-Si 1T-DRAM cell. In addition, we analyzed the memory mechanism and characteristics of this structure.

Approach for fabricating JLT using chemically deposited cadmium sulphide and titanium dioxide

Cadmium sulphide and titanium dioxide-based junctionless transistor (JLT) has been demonstrated by using simple and low-cost chemical bath deposition method. The morphological and structural study has been performed to speculate the crystallinity and the topography of individual layers of the proposed device. The optimised sputtering conditions lead to the formation of source and drain electrical contacts of the device. The fabricated device successfully functionalised as a p-channel JLT. At the source-to-drain voltage of −50 V, the ON-state drive current and OFF-state leakage current of the fabricated JLT are found to be −6 µA and 1.3 nA, respectively.

Negative capacitance δ ‐bulk planar junctionless transistor for low power applications

The impact of substrate doping on the short-channel effects (SCEs) of bulk-planar junctionless transistor (BPJLT) has been studied. It has been found that increasing substrate doping in bulk region reduces off-state leakage current (I OFF) and the sub-threshold slope (SS) of the device. To further reduce the SCEs of BPJLT heavily doped δ-layer of thickness 10 nm has been added below the channel. Despite the presence of δ-layer in BPJLT reduces SCEs, the SCE, mainly SS, is still limited by the fundamental limit of 60 mV/decade. Therefore, to reduce SS below 60 mV/decade, negative capacitance (NC) δ-BPJLT has been proposed by adding the layer of ferroelectric material at gate stack. It has been found that in comparison with conventional BPJLT and δ-BPJLT, the insertion of ferroelectric layer in NC-δ-BPJLT not only reduces the I OFF and the SS but also improves I ON/I OFF ratio of the device. Thus, embedding heavily doped δ-layer in the bulk region and the ferroelectric layer at the gate stack of BPJLT makes it a promising device for low-power applications.

A Complete Analytical Model of Surface Potential and Drain Current for an Ultra Short Channel Double Gate Asymmetric Junctionless Transistor

A Complete Analytical Model of Surface Potential and Drain Current for an Ultra Short Channel Double Gate Asymmetric Junctionless Transistor

A method for reduction of off state leakage current in symmetric DG JLT

A novel method for reduction of off state leakage current in a symmetric double gate junctionless transistor (DG JLT) is presented in this paper. In this technique a layer of dielectric has been placed at centre of the JLT. As major portion of leakage current flows through the centre, placing a dielectric at the centre will reduce the leakage current to large extent. An analytical model of drain current and threshold voltage for the proposed structure is developed. The model is validated by comparing it with simulation results obtained from TCAD (Technology Computer Aided Design). The model is in close agreement with TCAD results. The model as well as simulation results show that the JLT with dielectric layer placed at the centre has lower subthreshold current compared to the conventional JLT.

Performance assessment of symmetric double gate negative capacitance junctionless transistor with high-k spacer at elevated temperatures

The present work focuses on investigating the performance of short channel symmetric Double Gate Negative Capacitance Junctionless Transistor (DGNCJLT) with high-k spacers at elevated temperatures. The device behaviour has been explored for a temperature range of 300–380 K by obtaining self consistent solution based on standard Poisson’s equation, current continuity equation and Landau-Khalatnikov equation. The impact of high-k spacer lengths and dielectric constants has been explored on device behaviour at high temperature. Also, to alleviate the degradation in device behaviour at high temperature and to achieve sub-60 mV/dec operation even at elevated temperatures, optimisation of ferroelectric layer parameters has been done. It has been demonstrated that by optimising various parameters such as ferroelectric layer thickness, coercive field and remanent polarisation, device performance can be improved significantly even at high temperatures.

Bulk Junctionless Transistor (JLT) with non-uniform doping: A high performance and scalable device

In this paper we have presented the non-uniformly doped bulk Junction less transistor (JLT) and investigated bulk-JLT and SOI-JLT with non-uniform doping in terms of its electrical performance parameters and short channel effects (SCEs) parameters comparatively. Effective thickness of channel depends on non-uniform doping distribution parameters and this affects the performance of bulk-JLT notably, however it is not so in case of SOI-JLT. The effect of non-uniform doping on electrical characteristics of JLTs (bulk and SOI) in terms of Subthreshold Slope (SS), ON-current, OFF-Current and ON/OFF current ratio has been investigated, and the non-uniformly doped bulk-JLT exhibits high ON/OFF ratio (109 for 20 nm Gate Length). Moreover, the non-uniformly doped bulk-JLT also shows improved short-channel effects (SCEs) parameters (such as Drain Induced Barrier Lowering, Threshold Voltage variations etc.) compared to SOI-JLT. Lastly, the effect of standard deviation, dielectric constant, substrate doping, and well biasing on the device performance are examined to further improve the performance of bulk-JLT independently.

A Nano junctionless Double-Gate MOSFET by Using the Charge Plasma Concept to Improve Short-Channel Effects and Frequency Characteristics

In this study, a junctionless double-gate metal-oxide semiconductor field-effect transistor (MOSFET) is investigated by using the concept of charge plasma. The n+ charge plasma in source and drain regions is created electrically in the double-gate MOSFET (CPSD-MOSFET) using additional appropriate metals without applying doping. The results showed that the structure is like a conventional MOSFET, which can improve some electrical parameters. It protects the proposed structure from some limitations such as random doping oscillations and short-channel effects bearing its conventional structure. In addition, high temperature and annealing processes are unnecessary for making the source/drain doping of the CPSD-MOSFET because their regions are created electrically. Thus, the thermal budget step is removed. Furthermore, the proposed structure has some improvements as compared to the junctionless transistor structure, and it can overcome the main problem of this structure, namely the high off current. In general, in the proposed structure, the charge plasma idea changes the charges and depletion regions besides the channel and improves the short-channel effects such as hot electron effect and leakage current because of the improved electric field.

Quantum simulation of a junctionless carbon nanotube field-effect transistor under torsional strain

Abstract In this paper, a MOS-like junctionless carbon nanotube field effect transistor (JL-CNTFET) has been investigated. Energy band-gap and density of states (DOS) of carriers are two major parameters which are changed according to the torsional strain and affected the performance of JL-CNTFET. In this study, the effects of torsional strain on the analog (i.e., unity gain frequency (fT), transconductance (gm) and output resistance (rout)) and digital (i.e., OFF current, am-bipolar) characteristics of the device and also the switching behavior of the device have been studied and discussed. The simulation has been done using the non-equilibrium Green's function (NEGF) approach. The results show that torsional strain exerts significant effects on the electrical properties of the device and considering the multiple application of this transistor, it can also be used to improve the electrical properties of the transistor in specific applications.

3D Double-Gate Junctionless Nanowire Transistor-Based Pass Transistor Logic Circuits for Digital Applications

We investigate the circuit performance of the junctionless nanowire transistor. We have demonstrated pass transistor-based logic gates using the junctionless transistor. Pass transistor-based basic logic gates: AND, OR, XOR are designed using only the n-type junctionless nanowire transistor with HfO2 gate dielectric. Simulations of these circuits have been studied and analyzed under a mixed-mode environment. Outcomes of the analysis show that 3D dual gate junctionless nanowire transistor with 20 nm gate length well performed for pass transistor logic. In addition, a junctionless nanowire transistor-made multiplexer has also been studied and found to perform well. A high-k gate dielectric was used for all junctionless transistors as the higher k value improves the device characteristics and circuit performances. Our study also shows that the junctionless nanowire transistor-based pass transistor logics for digital circuit perform well.

Boosting the performance of an ultrascaled carbon nanotube junctionless tunnel field-effect transistor using an ungated region: NEGF simulation

This paper focuses on the role of the longitudinal spacing between the auxiliary gate and control gate in boosting the performance of an ultrascaled junctionless carbon nanotube tunnel field-effect transistor (JL CNT-TFET). The investigation is based on self-consistent quantum simulations in the nonequilibrium Green’s function formalism in the ballistic limit. It is found that dilation of the ungated longitudinal space between the gates causes a significant improvement in the leakage current, ambipolar behavior, subthreshold swing, on/off-current ratio, power–delay product, and intrinsic delay. In addition, a substantial enhancement in the swing factor and current ratio is also recorded for the JL CNT-TFET with coaxial control gate length below 10 nm. The results indicate that adjusting the spacing between the auxiliary gate and control gate is a simple, efficient, and promising approach to achieve ultrascaled JL CNT-TFETs with very high performance.