Junctionless Transistor Research Articles

Doping Dependent Assessment of Accumulation Mode and Junctionless FET for 1T DRAM

This paper demonstrates the use of double-gate accumulation mode (AM) and junctionless (JL) transistors for dynamic memory applications at 85 °C. The doping dependent assessments of AM and JL devices include an analysis of storage volume, carrier lifetime, and depth of potential well to determine characteristics of Dynamic Random Access Memory (DRAM). This paper shows significant impact of carrier lifetime for channel doping $({N}_{\text{d}}) \le 10^{ {18}}$ cm−3 on Retention Time (RT), while the depth of potential well is more critical at higher doping (>1018 cm−3). RT of ~2.5 s at 85 °C and ~4.5 s at 27 °C is achieved for gate length ( ${L}_{\text{g}}$ ) of 400 nm with ${N}_{\text{d}} = 10^{{17}}$ cm−3 which reduces to ~90 ms at 85 °C for ${L}_{\text{g}} = 25$ nm. This paper discusses the storage volume ( ${L}_{\text{g}} \times \text {film}$ thickness for a fixed volume with width of $1~ {\mu }\text{m}$ ) optimization to attain maximum retention. Insights and guidelines, as a function of doping and device dimensions, are outlined for dynamic memory applications.

A Model for Gate-Underlap-Dependent Short- Channel Effects in Junctionless MOSFET

In this paper, we investigate the impact of gate–source/drain underlap on short-channel behavior of junctionless (JL) transistor through a quasi-analytical model and 2-D numerical simulations. The proposed five-region model for potential is developed for the symmetric mode operation of double-gate (DG) JL MOSFET in the subthreshold regime, to predict and minimize short-channel effects (SCEs) using the optimum design of underlap regions. The five-region model can be transformed into four or three regions to incorporate the possible dependence of biases, doping, and gate workfunction with the underlap length. The parameters indicating SCEs can also be extracted using an analytical approximation for subthreshold drain current. The results from the proposed model are in reasonable agreement with simulation data. Analyses show that underlap length is a critical parameter to restrict the lateral extension of depletion region into the ungated portion. With increasing the underlap length, SCEs improve prominently for moderate doping concentration ( $10^{18}$ cm $^{-3}$ ). The improvement in SCEs ceases once the device achieves the maximum lateral extension of the depletion region. This paper provides the physical insights into the optimal use of underlap region in nanoscale JL devices for suppressing SCEs.

Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel

In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core.

Analytical modeling of split-gate junction-less transistor for a biosensor application

This paper represents the analytical modeling of split-gate Dielectric Modulated Junction Less Transistor (JLT) for label free electrical detection of bio molecules. Some part of the channel region is opened for providing the binding sites for the bio molecules unlike conventional MOSFET which is enclosed with the gate electrode. Due to this open area, the surface potential of this region affected by the charged and neutral bio molecules immobilized to the open region of channel. Surface potential of the channel region obtained by solving two-Dimensional Poisson's equation by potential profile having parabolic nature through channel region using technique called conformal mapping. By deriving the surface potential model, derivation of threshold model can also be done. For the detection of bio molecule, variation in to the threshold voltage due to binding of bio molecule in the gate underlap region is the sensing metric.

Nanoscale High-k Dielectrics for Junctionless Nanowire Transistor for Drain Current Analysis

Hafnium oxide (HfO2) nanoparticles were prepared by a chemical precipitation method and its physical and electrical properties were investigated. HfO2 thin films were prepared via a dip-coating method using the synthesized HfO2 nanoparticles. The crystallinity and resistivity of both prepared thin films were analysed by x-ray diffraction and impedance analyser. The crystalline size was found to be 8 nm and 13 nm for HfO2 and SiO2 thin films, respectively. The electrical (bulk) resistance was calculated by fitting the complex impedance plane using z-view software, and was found to be 2.15 × 107 Ω for HfO2, whereas it was found to be 3.6 × 105 Ω for SiO2 thin films. Junctionless nanowire transistors were implemented using HfO2 dielectric and performance was compared to SiO2 gate dielectric. The results revealed that nano-sized HfO2 proves to be a better gate dielectric material than conventional gate dielectrics. Thus, the nano-sized HfO2 based junctionless transistor device is more suitable for future low power applications.

Compact modeling of nanoscale triple-gate junctionless transistors covering drift-diffusion to quasi-ballistic carrier transport

In this work, we extend our analytical compact model for nanoscale junctionless triple-gate (JL TG) MOSFETs, capturing carrier transport from drift-diffusion to quasi-ballistic regime. This is based on a simple formulation of the low-field mobility extracted from experimental data using the Y-function method, taking into account the ballistic carrier motion and an increased carrier scattering in process-induced defects near the source/drain regions. The case of a Schottky junction in non-ideal ohmic contact at the drain side was also taken into account by modifying the threshold voltage and ideality factor of the JL transistor. The model is validated with experimental data for n-channel JL TG MOSFETs with channel length varying from 95 down to 25 nm. It can be easily implemented as a compact model for use in Spice circuit simulators.

Improved Thermal Stability and Stress Immunity in Highly Scalable Junctionless FETs Using Enhanced-Depletion Channels

In this work, we report a novel multi-PNPN-channel junctionless transistor with short channel length of 60nm. The multi-PNPN junctionless transistor exhibits the larger drive current of >1μA/μm, the steeper turn-on switching of 77 mV/decade, and the higher on/off current ratio of >107 than the hybrid PN channel device under the same gate overdrive. The improved performance is mainly attributed to the enhanced depletion effect of multi-PNPN channel to optimize the electric field modification of surface p-channel. The stronger immunity to constant-voltage stress is also obtained for multi-PNPN channel due to the lower lateral electric field near drain side to reduce the impact ionization ratio.

Junction‐less charge plasma TFET with dual drain work functionality for suppressing ambipolar nature and improving radio‐frequency performance

This work deals with a distinct concept to realise the junction-less tunnel field effect transistor (JL TFET) by creating the plasma of charges. The crux of this study is to reduce ambipolar conduction and to improve high-frequency figure of merits. To construct a JL TFET, initially P + silicon film is considered and then metal electrodes are used to form drain and channel region. The drain electrode is separated into two sections and the work function of section adjacent to channel is selected higher than the other section. This provides a non-uniform doping profile in the drain region creating large barrier at the drain/channel junction to prevent the ambipolar conduction. Ambipolarity is reduced to 1 × 10 -14 from 1 × 10 -8 at V gs = -1.5 V. The selection of work function and length of drain electrode adjunct to channel is crucial for optimising device performance. This optimisation provides information that work function >4.0 eV and length = 10 nm completely suppresses the ambipolarity which is around 1 × 10 -21 with little degradation in ON-current. The high work function for the section of drain electrode adjunct to channel provides lower gate-to-drain capacitance (~2.67 fF) and superior high-frequency responses. Furthermore, performance assessment at circuit level is done by implementing primary digital circuits as inverter and NAND logic with lookup table based Verilog-A model.

Hybrid N-Type Poly-Si Ultra-Thin Nanowire Shell Channel with P-Substrate Structure by Electron Beam Lithography Adjustment for Junctionless Field-Effect Transistors

This study proposes a new hybrid N channel/P substrate for junctionless field-effect transistors (JL-FET) by using electron beam lithography adjustment for the shell structure. The nanowire (NW) shell JL-FET exhibits the superior electrical properties, including high ON/OFF current ratio of 6 × 106, low subthreshold swing (SS) of 95 mV/decade and drain-induced barrier lowering value (DIBL) of 50 mV/V. This NW shell structure JL-FET is simple to fabricate, and highly favorable for use in advanced System-on-panel (SoP) and three-dimensional (3-D) stacked IC applications.

Efficient Layout Design of Junctionless Transistor Based 6-T SRAM Cell Using SOI Technology

In this work novel 6-T SRAM layout has been proposed using Junctionless SOI MOS transistor. The key idea of the proposed structure is to reduce the area consumed by the device with an aim to improve its performance. The junctionless SOI n- and p-MOS transistor exhibits lower off-state current and higher Ion to Ioff ratio when compared to double gate junctionless transistor available in the literature. In the proposed 6-T SRAM cell layout formation, an arrangement of latch circuit was done and later on two n-transistors back-to-back were cascaded to form a compact SRAM layout configuration. Thus, the proposed structure utilizes nearly half the area of conventional junctionless 6-T SRAM layout. The proposed design also shows improvement in delay time in read/write operations. The proposed structures were designed and simulated using Sentaurus and Cogenda device simulator.

A Graded Channel Dual-Material Gate Junctionless MOSFET for Analog Applications

This paper presents a graded channel dual material gate junctionless transistor (GC-DMGJLT) for analog applications. We studied various performance parameters of GC-DMGJLT and compared them with uniform channel dual material gate junctionless transistor (UC-DMGJLT) using Sentaurus TCAD device simulator. The simulation results specify the superiority of GC-DMGJLT that yields higher values of drain current (Id), transconductance (gm) and cut-off frequency (ft) at the cost of slight increase in output transconductance (gds). Furthermore, besides DIBL all other short channel parameters are also suppressed in graded channel device resulting in its superiority over uniform channel device.

Empirical Model for Nonuniformly Doped Symmetric Double-Gate Junctionless Transistor

This paper demonstrates the influence of nonuniform doping on the electrostatics of symmetric double-gate junctionless transistor using empirical modeling scheme. To present the clear insight into the device electrostatics of nonuniform doped channel, the peak of the doping concentration has been varied from Si/SiO2 interface of front gate to the back gate. The parameters explored in this paper are surface potential, electric field, drain current, threshold voltage, subthreshold slope, and drain-induced barrier lowering for different straggle factors and channel lengths. By properly optimizing the straggle value and peak of the doping concentration, device performance can be tuned accordingly.

InGaAs Junctionless FinFETs With Self-Aligned Ni-InGaAs S/D

In this paper, the InGaAs junctionless (JL) FinFET with notable electrical performance is demonstrated. The device with $W_{\mathrm{ fin}}$ down to 20 nm, EOT of 2.1 nm, and $L_{G} = 60$ nm shows high $I_{\mathrm{ ON}} = 188~\mu \text{A}/\mu \text{m}$ at $V_{DD} = 0.5$ V and $I_{\mathrm{ OFF}} = 100$ nA/ $\mu \text{m}$ , $I_{\mathrm{ ON}}/I_{\mathrm{ OFF}} = 5 \times 10^{5}$ , DIBL = 106 mV/V and SS = 96 mV/dec. The device also exhibits a decent extrinsic transconductance ( $G_{\mathrm{ m}}$ ) of 1142 $\mu \text{S}/\mu \text{m}$ at $V_{\mathrm{ DS}}$ of 0.5 V. This high performance is attributed to the moderate doping concentration to ensure the channel carriers could be effectively depleted and the low $R_{\mathrm{ SD}}$ realized by self-aligned Ni-InGaAs alloy S/D. Furthermore, we also examine the temperature dependence of the main electrical parameters of the JL transistor.

Series resistance in different operation regime of junctionless transistors

Operation mode dependent series resistance (Rsd) behavior of junctionless transistors (JLTs) has been discussed in detail. Rsd was increased for decreasing gate bias in bulk conduction regime, while a constant value of Rsd was found in accumulation operation mode. Those results were compared to conventional inversion-mode (IM) transistors, verified by 2D numerical simulation and temperature dependence of extracted Rsd. This work provides key information for a better understanding of JLT operation affected by Rsd effects with different state of conduction channel.

Steep-slope hysteresis-free negative capacitance MoS2 transistors.

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption 1,2 . Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier 3 . Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel 4-12 . Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

Extraction of mobility and Degradation coefficients in double gate junctionless transistors

In this work, we use the modified McLarty function to understand and extract accumulation (μacc) and bulk (μbulk) mobility in Double Gate (DG) Junctionless (JL) MOSFETs over a wide range of doping concentration (Nd) and temperature range (250 K to 520 K). The approach enables the estimation of mobility and its attenuation factors (θ1 and θ2) by a single method. The extracted results indicate that μacc can reach higher values than μbulk due to the screening effect. Results also show that θ2 extracted in the accumulation regime of JL transistors exhibit relatively low values in comparison to inversion and accumulation mode devices. It is shown that the attenuation factor (θ1) in JL devices designed with higher Nd (≥1019 cm−3) is mainly affected by series resistance (Rsd) whereas, in inversion mode (IM) and Accumulation mode (AM) devices, θ1 factor is governed by both the intrinsic mobility reduction factor (θ10) and Rsd. Additionally, the impact of variation in oxide thickness (Tox), gate length (Lg), Nd and temperature on θ1 and θ2 has been investigated for JL transistor. The weak dependence of μbulk and μacc on temperature shows the prevalence of coulomb scattering over phonon scattering for heavily doped JL transistors. The work provides insights into different modes of operation, extraction of mobility and attenuation factors which will be useful for the development of compact models for JL transistors.

Effect of Channel Width Variation on Electrical Characteristics of Double Lateral Gate Junctionless Transistors; A Numerical Study

In this paper, the effect of channel width variation on performance of double lateral gate junctionless transistors in the depletion and accumulation regimes is investigated. The characteristics of the device with various channel widths is comprehensively examined through analysis of on and off state current, threshold voltage (V th), transconductance (g m) and drain conductance (g D) variation in each operating regime. The carriers’ density distribution, electric field components and mobility are investigated through 3-D numerical simulations of the device to illustrate the variation of output characteristics. The results show that as the width decreases, the off-current (I OFF) decreases significantly as a result of better electrostatic control of the lateral gates over the channel. The on-current (I ON) is also decreased mainly due to the doping-dependent mobility degradation.It is also indicated that between the flat-band and fully depleted (pinch off) variation of the majority carriers is the main parameter that modifies the characteristics of the device, while the mobility variation is recognized as the basic factor in the accumulation regime.

Analytical model of nanoscale junctionless transistors towards controlling of short channel effects through source/drain underlap and channel thickness engineering

We develop a 2D analytical subthreshold model for nanoscale double-gate junctionless transistors (DGJLTs) with gate-source/drain underlap. The model is validated using well-calibrated TCAD simulation deck obtained by comparing experimental data in the literature. To analyze and control short-channel effects, we calculate the threshold voltage, drain induced barrier lowering (DIBL) and subthreshold swing of DGJLTs using our model and compare them with corresponding simulation value at channel length of 20 nm with channel thickness tSi ranging 5–10 nm, gate-source/drain underlap (LSD) values 0–7 nm and source/drain doping concentrations (NSD) ranging 5–12 × 1018 cm−3. As tSi reduces from 10 to 5 nm DIBL drops down from 42.5 to 0.42 mV/V at NSD = 1019 cm−3 and LSD = 5 nm in contrast to decrement from 71 to 4.57 mV/V without underlap. For a lower tSiDIBL increases marginally with increasing NSD. The subthreshold swing reduces more rapidly with thinning of channel thickness rather than increasing LSD or decreasing NSD.

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

Impact of thin high-k dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor

RF performance of 3D double gate junctionless transistor (JLT) is investigated considering thin high-k dielectrics and gate metals. The 3D double gate junctionless transistor (JLT) with 20nm gate length is designed and simulated in order to study the RF parameters such as transconductance, transconductance generation factor, output conductance and resistance, intrinsic capacitance, cut-off frequency, early voltage, and intrinsic gain. High-k dielectric gate oxide and gate metals have effect on the DC characteristics of JLT. However, in order to evaluate the impact of high-k gate dielectrics on the RF performance of the device, SiO2, Si3N4, HfO2 dielectrics are considered and compared their performances. Furthermore, the effect of various gate metals on RF performances of the device is also discussed. Gate oxide with higher-k value improves the transconductance, output conductance, and intrinsic gain of the device. While, gate metal with lower work function exhibits better RF characteristics in JLT, application of different high-k dielectrics and gate metal have no improvement in cut-off frequency. The investigation gives an idea to optimize the RF performance of the device using suitable gate dielectric and gate metal. This investigation helps to create an opportunity for the junctionless transistor to realize high performances RF circuits.