Junctionless Transistor Research Articles

Quantum Mechanical Analysis on Modeling of Surface Potential and Drain Current for Nanowire JLFET

This paper presents an analytical model for ultra scaled symmetric double gate (SDG) nanowire junctionless field effect transistor (JLFET), which includes charge quantization in all the regions of operation. This model is based on a first-order correction for the confined energies obtained by solving the Schrodinger’s equation. The model is able to predict the quantum mechanical effects (QME) on the surface potential, drain current and transconductance for a highly doped and extremely thin silicon layer of thickness down to 4nm. The results obtained are validated by comparing with GENIUS 3D TCAD quantum simulations.

Effect of transient behavior on off-state current in poly-Si junctionless nanowire thin-film transistor

For forward sweeping of V GS, the unpredicted negative drain current is observed in our L-type double-gated junctionless transistor. This reveals that in addition to gate-induced drain leakage, there is an another mechanism that causes this negative drain current. According to some measurements, it is found that the negative drain current is related to the steep V GS transition, and the large reduction of hole density in the nanowire channel induces a transient negative drain current. Based on this mechanism, for reverse sweeping of V GS, the positive drain current is measured due to an increment of hole density in the nanowire channel. To explain the mechanism well, the hole density in the Si channel is simulated and an AC model is proposed. Finally, it is likely that the transient negative current of the drain is also affected by the gate transient current, besides the large reduction of hole density.

Novel Dual-Metal Junctionless Nanotube Field-Effect Transistors for Improved Analog and Low-Noise Applications

Dual-metal junctionless nanotube field-effect transistors (DMJN-TFETs) for improvised analog and digital applications are described. It has been realized that, compared with existing junctionless nanowire FETs, in particular, junctionless-gate all around (J-GAA) metal oxide semiconductors (MOS) FETs, dual-metal junctionless-gate all around (DMJ-GAA) MOSFETs, and junctionless nanotube (JN) FETs, DMJN-TFET MOSFETs exhibit higher Ids, gm, gd and fT compared with the JNFETs, making it a favorable device for high-frequency analog FET applications. DMJN TFETs exhibit a surpassing ION/IOFF ratio, with the subthreshold slope approaching the ideal values, a mitigated device channel resistance (Rch), advanced early voltage (VEA), a higher transconductance generation factor, maximum transducer power gain, unilateral power gain, and minimized noise conductivity and noise figure. Also, the small signal metrics including the transmission coefficients (S21 and S12) and reflection coefficients (S11 and S22) have been investigated to authenticate the small signal conduct of our device. These improvised characteristics make a DMJN-TFET the most suitable device design for both digital and analog applications employing FETs.

Room temperature terahertz detector based on single silicon nanowire junctionless transistor with high detectivity

In this work, the n-type single silicon nanowire (NW) based junctionless field-effect transistor (FET) is demonstrated as an efficient terahertz (THz) detector. For the effective coupling of the THz radiations with NW junctionless FET, the lobes of the rounded bow-tie antenna are connected to the gate and source terminals of the device. The antenna design is optimized with proper impedance matching conditions to achieve maximum power transfer between antenna and detector. The simulated antenna resonates at 0.43 THz frequency with 19 GHz bandwidth. Further simulations have been done on Lumerical finite difference time domain software to analyze the electric field distribution profile. To investigate the optical response of this optimized antenna design, an array of the simulated antenna has been fabricated and its transmission spectra are measured. Finally, the simulated antenna has been integrated with the n-type NW junctionless transistor. A maximum responsivity of 468 V W−1 at 0.425 THz frequency and noise-equivalent-power of ∼ 10−9W/Hz1/2 is obtained at room temperature. The complementary metal-oxide-semiconductor’s compatibility, ease of integration on chips, possibility to realize multiple pixel arrays, andscalability to higher frequencies, make this device promising for THz electronics.

Controlling the Effective Channel Thickness of Junctionless Transistors by Substrate Bias

Substrate-bias-affected unique electrical characteristics of junctionless transistors (JLTs) were investigated in detail. Bulk channel thickness of JLTs (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">si_eff</sub> ) was effectively modulated by back-gate bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> ). The variation in threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) and mobility degradation were observed in the reduced t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">si_eff</sub> , due to the negative V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> -induced depletion of free electrons. The V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> effect was also influenced significantly by the doping concentration in JLTs. In addition, numerical simulations verified those results and analytical equations explained well the experimental results.

Design and Investigation of Split-Gate MoTe2-Based FET as Single Transistor AND Gate Using Nonequilibrium Green’s Function

Failure of metal–oxide–semiconductor field-effect transistor (MOSFET) in the nanometer regime has raised concern for the researchers. Although researchers have provided solutions in the form of tunnel FETs and junctionless transistors but due to their fabrication issues, MOSFET remains as the backbone of the very large-scale integration (VLSI) industry. This work is dedicated to the design and study of the novel split-gate MOSFET made up of transition metal dichalcogenide. The proposed design can help in realizing digital gates because the device is used as a single transistor AND gate in this work. The device is analyzed for different conditions like the variation in work function, variation in gate length, variation in spacer oxide, and effect of interface trap charge (ITC) density. Nonequilibrium Green’s Function is used as an elemental model of the transistor to include quantum effects for scaled-down dimensions. This work shows that the proposed device results in a noticeable flow of current only when both the gate terminals are at higher potential, that is, at state “11.” The observed linearity is good enough for the efficient working of the device. Hence, the device can be utilized as AND gate with a lesser area and power dissipation.

Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer.

Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage

AbstractThis work reports contact engineered charge plasma junctionless transistor (CE‐CP‐JLT) to suppress the tunneling leakage current by deploying calibrated exhaustive 2‐D TCAD simulations. This analysis considered the detrimental effect due to the nonohmic source and drain side contacts by including universal Schottky tunneling and band‐to‐band tunneling models. Our study suggests to reduce the source/drain metal contacts to control the carriers tunneling in OFF state. This contact engineering can effectively minimizes the leakage with retained drive current capabilities. This would in turn improve the device switching behavior and ION/IOFF current ratio at least by four orders. The reduction in leakage current leads to decrease in static power consumption. This facilitates the CE‐CP‐JLT deployment in a portable device for longer duration with same power supply. Further, the device sensitivity analysis with respect to electrode contact length, gate oxide thickness, dielectric constant, channel length and silicon film thickness is also analyzed. Moreover, the comparative analysis of device analog behavior is also carried out here.

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs.

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

A new state of the art double gate junctionless transistor (DGJLT) namely the rectangular core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to investigate the performance. An RCS-DGJLT device is designed using a visual technology computer aided design tool and look up table-based Verilog-A model has been designed to carry out spice simulation of the circuit. Device simulation of RCS-DGJLT shows the extraordinary performance when compared to conventional DGJLT. The RCS-DGJLT exhibits an OFF current (Ioff ) ∼10−14 A, ON current (Ion ) ∼10−5 A, ON/OFF current ratio (Ion /Ioff ) ∼109, subthreshold slope ∼68.9 mV decade−1 and drain induced barrier lowering ∼52.6 mV V−1. Also, the AC response of RCS-DGJLT exhibits good performance like lower miller capacitances of order 10–16 F, maximum unity gain frequency of 138.8 GHz, transconductance generation efficiency of 40 V−1, and gain-bandwidth product of 25.4 GHz. The common source amplifier circuit using RCS-DGJLT provides the amplification up to 3.3 times which implies gain (Av ) to be 3.3. The low leakage power of 10.4 pW and average power of 31.2 µW of common source amplifier circuit based on RCS-DGJLT shows the greater potential of using the proposed device in analog applications. Also, the complete flow chart of the process used to design an analog circuit based on proposed RCS-DGJLT is discussed. The result shows the potential of using the RCS-DGJLT device in designing high-frequency applications.

Simple estimation of intrinsic electrical parameters in junctionless transistors

Junctionless transistors (JLTs) are an attractive candidate for advanced complementary metal oxide semiconductor technologies, but their mode of operation is very different from that of conventional inversion-mode transistors. In this study, we explore the close relationship between the key electrical parameters of JLTs, such as doping concentration (Nd), threshold voltage (Vth), and flat-band voltage (Vfb). The separation between Vfb and Vth in JLTs increases linearly with Nd, and the rate of increase in the separation was affected by the maximum depletion depth (Dmax) at given Nd. These findings will enable researchers to estimate simply the Nd or Vfb values of not only JLTs but also JLT-like multi-layer transition metal dichalcogenide-based transistors.

Effects of Work-function Variation on Performance of Junctionless and Inversion-mode Dual-metal Gate Nanowire Transistors

Effects of Work-function Variation on Performance of Junctionless and Inversion-mode Dual-metal Gate Nanowire Transistors

Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-K Dielectrics and Gate Metals

The paper presents the investigation of linearity distortion analysis of double gate junctionless transistor with high-k gate dielectrics and gate metals. As double gate junctionless transistors have shown high performance in digital circuits, linearity analysis is carried out to understand nonlinear behavior of the device for RFIC applications. In order to ensure minimum intermodulation and higher order harmonics at the system output, different linearity parameters like Second Order Voltage Intercept Point, Third Order distortion, Third Order Input Intercept Point and Third Order Intermodulation Distortion are evaluated. The results show that junctionless transistor should be biased at appropriate low voltage to ensure better linearity which is desired for RFICs. The effects of high-k gate dielectrics and gate metals on linearity characteristics of junctionless transistor are also investigated. Deterioration of the linearity is observed in junctionless transistor for the use of high-k insulators as gate dielectrics. It is also observed that low work function gate material is suitable to achieve higher linearity in low power applications.

A Study on Sensitivity of Some Switching Parameters of JLT to Structural Parameters

Background: The stringent technological constraints imposed by the requirement of ultra-sharp doping profiles associated with the sub-30 nm regime has led to the search for alternatives to the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET). An obvious alternative is a device whose architecture does not have any junctions in the sourcechannel- drain path. One such device is the Junctionless transistor comprising of an isolated ultrathin highly doped semiconductor layer whose volume is fully depleted in the OFF state and is around flat- band in the ON state. Such a structure overcomes the stringent technological requirement of an ultra-sharp grading profile required for nano-scale MOSFETs. For widespread application in today’s high-speed circuits, a key factor would be its effectiveness as a switch. Methods: In this work we have studied the relative sensitivity of two such parameters namely the ION/IOFF ratio and gate capacitance to variations in several structural parameters of the device namely channel width, composition of the dielectric layer, material composition of the channel region (i.e. Si vis-à-vis SiGe), doping concentration of the channel region and non-uniformity in the doping profile. Results: The work demonstrates through device simulations that replacement of Si with Si-Ge leads to an improvement in the performance. Conclusion: The most notable change has been observed by using a vertically graded doping profile as opposed to the original proposed uniformly doped channel.

Design and Investigation of Junctionless DGTFET for Biological Molecule Recognition

This work utilizes the dielectric modulated detection technique within a junctionless tunnel field-effect transistor (JLTFET) to detect various charged and neutral biomolecules. The electrostatic properties of the proposed dielectric modulated junctionless double gate JLTFET (DM-JL DGTFET) are observed and analyzed to determine the biomolecules like uricase (k = 1.54), Glucose oxidase (k = 3.46), APTES (k = 3.57), keratin (k = 8) and gelatin (k = 14) lipid, carbohydrate, nucleic acid (DNA and RNA), and protein, etc. The SiO2 (gate oxide) is etched and a cavity is shaped under the gate electrode in which the analytes are injected and thus the effective dielectric of the gate oxide is modulated. The injected charge or neutral analytes of the various biomolecules in the immobilized states are responsible to change the electrostatic characteristics of the DM-JL DGTFET device by varying the gate capacitance. The drain current, ION/IOFF, subthreshold slope, and sensitivity of the DM-JL DGTFET are estimated to recognize the biomolecules. The DM-DGJLTFET shows noticeable sensitivity outcomes 15.2 × 1011 for the charged biomolecules, especially the positively charged analytes.

DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor

With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model .This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity . The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversion-mode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion / Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV / V.

Junctionless Transistors: State-of-the-Art

Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

Performance Assessment of CMOS circuits using III-V on Insulator MOS Transistors

In this work, with the help of extensive technology computer-aided design simulations, we report a comprehensive study of MOSFET based circuit design using ultra-thin body III-V on-insulator (OI) CMOS transistors. We demonstrate the circuit performance of III-V CMOS by combining InAs-OI n-channel and GaAs-OI junction-less p-channel transistors. The performance metrics of different circuits designed using III-V transistors are also compared with III-V/Germanium and Silicon-on-insulator (SOI) based CMOS logic. CMOS inverter circuit designed using III-V/Ge (InAs-OI/GeOI) CMOS shows 51% and 17% reduction in rise and fall time compared to SOI CMOS. The oscillation frequency of the ring oscillator designed using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) CMOS logic is approximately three times and two times higher than SOI based design. The unity-gain bandwidth of the inverting amplifier using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) architecture is 22 times and 9.5 times higher compared to SOI CMOS based circuit. Static noise margin (SNM) of conventional six-transistor (6-T) SRAM cell is also analyzed during hold operation. Due to the poor electrostatic integrity of III-V transistors, degradation in SNM is observed compared to its SOI counterparts. The cascode low noise amplifier (LNA) circuit designed using InAs-OI transistor shows the higher gain and low noise figure at the same operating frequency compared to the SOI transistor-based LNA.

Channel width dependent subthreshold operation of tri-gate junctionless transistors

Junctionless transistors (JLTs) are one of attractive candidates for further scaling down thanks to their promising advantages based on a structural simplicity without PN junctions, and their physical operation is quite different from traditional inversion-mode (IM) transistors. In this paper, we investigated the subthreshold operation of tri-gate JLTs with various effective width (Weff) and compared to that of IM transistors. The on current to off current ratio (Ion/Ioff) and subthreshold swing (SS) of JLTs were varied dramatically as changing Weff. In addition, a better immunity against short channel effects (SCEs) of JLTs was proven. Physical operation mechanism on the subthreshold regime was also discussed in detail with considering distribution of mobile charge carriers, maximum depletion width, full-depletion mode, bulk neutral and surface accumulation conduction.

Impact of Pocket Doping On the Performance of Planar SOI Junctionless Transistor

In this paper, a novel sturcture of planar Silicon on Insulator Junctionless transistor is proposed with improved ION/IOFF ratio, Short Channel effects (SCEs) and most importantly, it is scaleable. A highly doped pocket (p-type) will form PN junction at its interface with n-type channel and hence referred to as pocket doped Silicon on Insulator Junctionless transistor (PD-SOI-JLT). A highly doped region in the channel helps to produce full depletion in the OFF state. A 2D Calibrated simulation study has shown an ION/IOFF ratio 105 in PD-SOI-JLT device comapred to conventional SOI-JLT device for gate length of 20 nm. Further, the use of PN junction isolation reduces the lateral electric field and hence improves the SCE performance of the proposed device as compared to conventional SOI-JLT. Besides this, the ac analysis has shown that the transconductance and Cutoff Frequency of the proposed device is at par with the conventional device.