Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture

Abstract

This paper proposes a p-type double gate junctionless field effect transistor having opposite doping in the core with that of the silicon body referring to rectangular core–shell (RCS) architecture. The use of RCS has significantly reduced the gate induced drain leakage and therefore, obtaining improved performance parameters. It is observed that the parasitic BJT action gets diminished in RCS architecture due to enlargement of tunneling width at the channel/drain interface. Further, after validating our simulations with the experimental results of junctionless p-type FET we demonstrated that insertion of oppositely doped core in silicon body helps to achieve volume depletion in OFF state. The simulation results show that junctionless FET with RCS architecture exhibit lower OFF current, higher ON/OFF ratio, better drain induced barrier lowering (DIBL) and superior subthreshold slope (SS) at lesser channel lengths. The measured values of OFF current, ON current, ON/OFF ratio, DIBL and SS at channel length 20 nm for RCS architecture are −9.96 × 10−15 A, −2.33 × 10−5 A, 0.23 × 1010, 42.1 mV V−1 and 67.7 mV/decade respectively. Interestingly, we have found a correlation between RCS thickness and channel length. Finally, a complementary metal oxide semiconductor (CMOS) inverter with RCS architecture is also designed. The voltage transfer characteristics of RCS based CMOS has been significantly improved as compared to the conventional junctionless CMOS inverter.