Abstract
This paper presents, a simulation based study of Double Gate Junctionless Field Effect Transistor (DG-JLFETs) with Vertical Gaussian Doping profile. The proposed device structure improves the ON to OFF drain current ratio (by ≈ 105), threshold voltage roll off (by ≈ 30 mV), Drain Induced Barrier Lowering (DIBL) (by ≈ 29 mV/V) and Sub-threshold swing (by ≈ 6 mV/dec at straggle parameter σ ≈ 3.75 nm in comparison to uniformly doped channel double gate junctionless Field effect transistors.
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