Characterization of Symmetric and Asymmetric Double Gate Junctionless Field Effect Transistor in Subthreshold Region

Abstract

In this work, we have analyzed the performance of symmetric and asymmetric structures of double gate junctionless field effect transistor (DG JLFET) in subthreshold region. In order to find out the characteristic parameters, we have used SILVACO ATLAS simulator. Different performance parameters like I-V characteristic, on state off state current ratio (Ion/Ioff), subthreshold swing (SS), drain induced barrier lowering (DIBL), threshold voltage (Vth) are explored from simulation model. These parameters are compared between different structures of the device. We have explored the behavior difference of the device by changing gate length (Lg), bottom gate oxide thickness (tox2), bottom gate electrode materials. Almost ideal DIBL and SS properties are found for both symmetric and asymmetric device structures in channel length of 50 nm. Symmetric DG JLFET has shown good short channel effect, but asymmetric device having lower bottom gate oxide thickness has shown more better short channel property.