Abstract
A novel method for reduction of off state leakage current in a symmetric double gate junctionless transistor (DG JLT) is presented in this paper. In this technique a layer of dielectric has been placed at centre of the JLT. As major portion of leakage current flows through the centre, placing a dielectric at the centre will reduce the leakage current to large extent. An analytical model of drain current and threshold voltage for the proposed structure is developed. The model is validated by comparing it with simulation results obtained from TCAD (Technology Computer Aided Design). The model is in close agreement with TCAD results. The model as well as simulation results show that the JLT with dielectric layer placed at the centre has lower subthreshold current compared to the conventional JLT.
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