Semiconductor Packaging Research Articles

Specialized Wirebond Process Configuration on Advanced Multi-Die Package

Wirebonding process is one important assembly process responsible for providing electrical connections between the silicon die and the external leads of a semiconductor package or device. The process also brings along some challenges as the device becomes more complex and critical. This paper is focused on the prevention of the broken wire on neck during wirebonding process of an advanced semiconductor package with multi-die configuration. Extensive wire loop character-ization and optimization was done and a specialized wirebonding configuration solution was formulated. Ultimately, the solution prevented high loop and wire sagging that could touch or short-circuit the silicon die. For future works, the configuration could be applied on packages with comparable construction.

Wafer Saw Process Optimization for Die Chipping Mitigation on Extremely Small Leadframe Package

The paper focused in addressing the silicon die chippings defect at the wafer sawing process of an extremely small semiconductor package. In-depth potential risk analysis and Pareto diagram were done to identify the top reject contributors and eventually resolve the issue. A comprehensive design of experiment (DOE) was done and validation of the solution was employed to formulate the effective corrective actions. Results revealed that die chippings were addressed by optimizing the wafer sawing process through enabling the dressing, pre-cut and step-cutting modes. Ultimately, an improvement of 95% for die chippings reduction was achieved.

Deep ultraviolet excimer laser processing for the micro via hole on semiconductor package

Moore's law has almost reached the limit of resolution on semiconductor die and, therefore, multidie packaging is one of the alternative solutions. Substrate materials currently use organic build-up films and silicon substrates [through silicon via (TSV)] in applications. But recently, organic films, too, have reached the resolution limit, and TSV is expensive. In this situation, nonalkali glass (glass) and fused silica (SiO2) substrates are expected to be good alternatives in high-frequency signal transfer applications like 5G telecommunication. But the via holes are hard to process with less defects (tips and cracks) on the glass and SiO2 substrates. Deep ultraviolet (DUV) excimer laser ablation is expected to have a finer (<10 μm) resolution with a shorter wavelength (248–193 nm) and also hard material processing with a higher photon energy (5–6.4 eV). Therefore, the authors have explored the application of the DUV excimer laser ablation process for a via hole on hard materials like glass and SiO2 substrates. In this study, they have investigated the via hole quality through the DUV excimer laser ablation process. The results show the possibilities of micromachining on both glass and SiO2 substrates. The authors have succeeded by achieving a value of <50 μm through the via hole grid aspect ratio of 6 on the glass substrate without any significant defects. As the ablation rate is quite an affordable value, DUV excimer lasers are expected to play a crucial role in the next-generation manufacturing process for semiconductor packages. The authors also investigate the SiO2 substrate with DUV excimer lasers.

Electrochemical Express Analysis of Organic Additives in Lead-Free Wafer Level Packaging Plating Baths

Semiconductor packaging migrated from wire bond to flip chip level interconnect to meet size, weight and electrical performance requirements. Lead-free alloys for flip chip attachment has become a common material in electronics. Alloys containing Sn and Ag as well as pure Sn are the most common ones. The mechanical strength, wetting, and fatigue resistance of these alloys and pure Sn is either comparable or surpass lead contained alloys. Electroplating with lead-free alloys is the most desirable technique due to its low cost and usefulness in building fine pitch solder bumps [1].The new generation of lead free plating systems targeting faster deposition rates, better uniformity with-in die and longer bath life. The co-deposition of elements may be complicated by the large difference in the electrode potentials of tin and alloying metals (e.g. silver, bismuth). To produce uniform and dense deposits, these plating baths include organic additives that are typically separated for two groups with different functions: polarizers that significantly affect the plating rate and control the uniformity of deposit; and grain refiners [2]. For desired properties of deposit, the bath components must be kept within specific concentration ranges. In some cases, the analytical results for bath components should be available more frequently in order to provide feedback to dosing system [3]. To develop most accurate and repeatable analytical methods, the interactions between lead free plating bath components were previously investigated and understood [2]. That allowed to develop efficient analytical techniques for analysis of lead free plating bath components. However, faster analytical methods are required for control of high speed plating baths. The effect of changes in the concentration of organic components on the structure of deposit were studied more recently and will be reported in this work.When the speed of analyses increases, it is critical to keep reproducible state of all electrodes. Therefore, new regeneration method for electrodes was developed. For development of new express analytical methods, we utilized an electrochemical cell with three electrodes connected to a potentiostat/galvanostat. RDE working and counter platinum electrodes were used as well as Ag/AgCl double junction reference electrode. It has been found that multiple factors can reduce the speed of electrochemical analysis. One of the most potent parameters that affect speed of analysis was a scan rate. Fig. 1 shows the electrochemical responses of polarizer at different scan rates.Other parameters and steps of analysis were also evaluated for potential reduction the analysis time. This presentation will provide more information related to the electrochemical behavior of organic additives at specific conditions when the analysis is performed with different speed. Results for other bath components will be also presented. The concentration of inorganic components and silver complexing agent can be determined via non-reagent and virtually real time spectroscopic analytical methods. The presentation will be concluded with a discussion of analytical results for several organic additives at different concentration levels.

Electroless Ni/Pd/Au Plating for Semiconductor Package Substrates (III) —Influence of the Electroless Pd Plating Thickness on the Solder Ball Joint Reliability and the IMC Growth—

Electroless Ni/Pd/Au Plating for Semiconductor Package Substrates (III) —Influence of the Electroless Pd Plating Thickness on the Solder Ball Joint Reliability and the IMC Growth—

반도체 패키지 검사 공정의 데이터 변화 감지를 통한 불량 예측 모델의 갱신

반도체 패키지 검사 공정의 데이터 변화 감지를 통한 불량 예측 모델의 갱신

Backside Metallization of Ag–Sn–Ag Multilayer Thin Films and Die Attach for Semiconductor Applications

Backside metallization, which offers the advantages of a thin die-attach layer, excellent ohmic contacts, good thermal dissipation, and electrical conduction, is a reliable die-attach method for high-temperature semiconductor devices. Optimized Ag–Sn–Ag thin film structures have been deposited as a backside metal layer and their mechanical and electrical characteristics evaluated as a replacement for conventional Au-based backside metal. The results confirmed that the Ag/Sn/Ag sandwich structure provided more reliable properties than the Sn/Ag and Ag/Sn structures. After the die-bonding process using the Ag/Sn/Ag backside metal, Cu6Sn5, Cu3Sn, and Ag3Sn intermetallic compounds were observed at the interface between the Si chip and Cu-plated Alloy 42 lead frame. The shear strength of the Ag/Sn/Ag backside metal was superior to that of conventional Au-12Ge backside metal, and its electrical characteristics met the requirement specifications of a commercial discrete semiconductor package.

Approaches for Measurement System Analysis Considering Randomness and Fuzziness

For some quality inspection practices, subjective judgements based on the inspectors' experience and knowledge, such as visual inspection, may be required for some particular quality characteristics. This kind of measurement system, including its associated randomness and fuzziness, should be assessed by Measurement system analysis (MSA) before its application. For such purpose, this article represents observations with randomness and fuzziness from MSAs as fuzzy random variables, and then two pairs of descriptive parameters, i.e., expected value and variance, are derived. Then, the relationship of the total sum of squares of factors is proven to hold, so that fuzzy analysis of variance (FANOVA) in terms of gauge repeatability and reproducibility can be developed. The proposed approach has the advantage that FANOVA is developed based on the relationship of the total sum of squares of factors, considering randomness and fuzziness. A real case in the semiconductor packaging industry is used to demonstrate the applicability of the proposed approaches to MSA.

Process Enhancement to Eliminate Adhesive Film Remains during Die Picking

Adhesive film remains on the dicing tape is one of the problems encountered in diebonding or die attach process during the pick-up process of silicon dies. With this occurrence, one method used to identify the root cause is the process mapping from wafer preparation to diebonding. Adhesive film remains are found occurring during the process, affecting the manufacturability and assembly yield of the semiconductor package. By resorting to a new and improved die attach adhesive film material, occurrence of its remains was mitigated during the diebonding process.

Interconnect Technique for Tight Clearance in Stacked-die Package

The paper focused in addressing wire-related assembly issues due to tight clearances in the semiconductor package design. Package design characterization was done considering the assembly design rules and the advanced rules, resulting to the integration of an interposer in the package design. With the new design, the assembly limitations and capability could be improved specifically for semiconductor devices with tight clearance requirement. Furthermore, gross assembly rejections related to tight clearances could be mitigated with the design solution and process improvement.

New Electronic Architectures

With the slowing of traditional semiconductor scaling, specialized processors, packaging and communication between chips has assumed increasing importance in meeting the needs of big data, IoT, and AI markets that will explode in the 2020 decade. Semiconductor designers are looking for new ways to provide the increasing computing capability needed to support our data intensive future. This led to multicore processors, processor accelerators, and the concept of chiplets and high-density interconnects.

Recent advances and trend of HEV/EV‐oriented power semiconductors – an overview

This study introduces the development advances and trend of power semiconductors used in hybrid and electric vehicles (HEV/EV). The status and forecast of power electronics’ requirement in HEV/EV are discussed along with a review of the automotive standard of power semiconductor devices. The advances in automotive semiconductor technologies such as Si-based insulated-gate bipolar transistor (IGBT) and freewheeling diode (FRD) and SiC-based metal oxide semiconductor field-effect transistor (MOSFET) and Schottky barrier diode are presented. The advances in automotive semiconductor packaging technologies are illustrated from three considerations, which are the low inductance in high-power density packaging, lower thermal resistance designing, and advanced packaging technologies. The challenges and development trend of more reliable power semiconductors for HEV/EV are discussed. The challenges in Si devices are focused on power density, efficiency, reliability, and packages, while the high temperature and low inductances are the main challenges for SiC devices. Lastly, the development trend is discussed in terms of four aspects, the new generation Si IGBT for HEV/EV, such as recessed-emitter-trench, reverse-conduction-IGBT, and smart IGBT; next generation SiC MOSFET; new packaging technology and material, such as planar packaging.

Bis-(sodium sulfoethyl)-disulfide: A Promising Accelerator for Super-conformal Copper Electrodeposition with Wide Operating Concentration Ranges

Accelerators are indispensable additives for super-conformal copper electrodeposition, which has been widely applied in the fabrication of integrated circuits (ICs), printed circuit boards (PCBs), and advanced semiconductor packaging substrates. Currently, bis-(sodium sulfopropyl)-disulfide (SPS) and sodium 3-mercapto-1-propanesulfonate (MPS) are the most widely used accelerators for super-conformal electroplating. However, owing to the limited operating concentration range, frequent measurements of the SPS (or MPS) concentration during the electroplating process are needed to manage the accelerator concentration in a suitable range, which makes the application of SPS (or MPS) tedious and unreliable. In our previous study, bis-(sodium sulfoethyl)-disulfide (SES), which has a molecular structure that is similar to that of SPS but with shorter alkyl chains, was determined to be a weaker depolarizer than SPS. The weaker antagonistic effect against suppressor and leveler imply that the higher concentration of SES maybe applicable to achieve the super-conformal electroplating. In this study, SES was investigated in detail, and it was found that in combination with Cl−, PEG, and JGB, the SES-containing electrolytes can provide the positive potential difference Δη, excellent microvia filling performance, and good copper deposition physical properties in a wide operating concentration range. SES is a promising accelerator for the super-conformal copper electroplating.

Incorporating Package Grinding Process for QFN Thin Device Manufacturing

Package thinning, down-scaling, and miniaturization are common interests among semiconductor industries, with each manufacturing site having different approach and technical directions in providing novelties in their products. The paper offers an innovative design of manufacturing flow to reduce the semiconductor package height of a Quad-Flat No-leads (QFN) device through the application of a specialized package grinding process. The process would significantly reduce the carrier thickness for the overall package height configuration of QFN. Through this integration, the common assembly barriers and defects related in producing thin devices are eliminated, thus thinner version manufacturing becomes more simplified and efficient.

A Reinforcement Learning Approach to Robust Scheduling of Semiconductor Manufacturing Facilities

As semiconductor manufacturers, recently, have focused on producing multichip products (MCPs), scheduling semiconductor manufacturing operations become complicated due to the constraints related to reentrant production flows, sequence-dependent setups, and alternative machines. At the same time, the scheduling problems need to be solved frequently to effectively manage the variabilities in production requirements, available machines, and initial setup status. To minimize the makespan for an MCP scheduling problem, we propose a setup change scheduling method using reinforcement learning (RL) in which each agent determines setup decisions in a decentralized manner and learns a centralized policy by sharing a neural network among the agents to deal with the changes in the number of machines. Furthermore, novel definitions of state, action, and reward are proposed to address the variabilities in production requirements and initial setup status. Numerical experiments demonstrate that the proposed approach outperforms the rule-based, metaheuristic, and other RL methods in terms of the makespan while incurring shorter computation time than the metaheuristics considered. Note to Practitioners —This article studies a scheduling problem for die attach and wire bonding stages of a semiconductor packaging line. Due to the variabilities in production requirements, the number of available machines, and initial setup status, it is challenging for a scheduler to produce high-quality schedules within a specific time limit using existing approaches. In this article, a new scheduling method using reinforcement learning is proposed to enhance the robustness against the variabilities while achieving performance improvements. To verify the robustness of the proposed method, neural networks (NNs) trained on small-scale scheduling problems are used to solve large-scale scheduling problems. Experimental results show that the proposed method outperforms the existing approaches while requiring a short computation time. Furthermore, the trained NN performs well in solving unseen real-world scale problems even under stochastic processing time, suggesting the viability of the proposed method for real-world semiconductor packaging lines.

Novel Pre-Applied Underfill Material Designed for Collective Bonding Process

Internet of Things (IoT) accelerated by the rapid progress of 5G is bringing a lot of challenges to semiconductor packaging technologies. In particular, flip-chip bonding technology is strongly required to realize ultrafine-pitch products, such as network, graphic, and artificial intelligence (AI) processors. Thermal compression bonding (TCB) with pre-applied underfill materials, such as nonconductive paste or nonconductive film (NCF), has been expected as one of the effective solutions for these applications for a long time. Nevertheless, the actual availability is still limited due to its high process cost. In other words, innovative breakthrough to achieve reasonable TCB cost is necessary to support the expansion of IoT. So far, some kinds of multiple die bonding processes represented by collective bonding have been proposed and demonstrated with conventional NCFs. However, it is becoming clear that the conventional NCFs optimized as fast cure type are very difficult to have enough processability for the multiple bonding processes due to mismatch between reactivities of the materials and bonding process conditions. That is why the new NCF dedicated to the multiple die bonding processes has been developed in this article. The developed NCF was designed to survive long-time thermal exposure on a bonding stage so that the collective bonding could be completed with reasonable process margin. To achieve target specifications, this article has started with the design of a new resin composition applied to the developed NCF. Then, basic properties required for NCFs, such as thermal stability and electrical insulation, were investigated in feasibility studies. Finally, TCB was demonstrated, and reliable solder joints were formed without any abnormality even after extended thermal exposure on the bonding stage. Moreover, it was found that the developed NCF might have the potential to achieve void-free encapsulation by pressure curing.

A Novel Dicing tape for WLCSP Using Stealth Dicing Through Dicing tape and Back Side Protection-Film

Abstract Market demand of information terminals for Internet of Things (IoT) is increasing. So market situation requires various semiconductor packages. Wafer Level Chip Size Package (WLCSP) is one of the most important technology among them. We selected stealth dicing (SD) as a manufacturing method for WLCSP because the cutting speed is higher than blade dicing and the yield of semiconductor chip is higher than blade dicing. But, SD process still has some technical issues. In some cases, when the laser is irradiated from circuit side (from surface side of Si wafer), the metal pattern in circuit might prevent the laser focusing. In this case, the laser should be irradiated from backside of Si wafer through dicing tape. We have already developed a transparency suitable dicing tape for the SD process, but the base film material of the dicing tape is poly vinyl chloride (PVC) which is not becoming to conform with some of recent environmental standard. Market situation requires poly olefin (PO) dicing tape because of global environmental consideration. We developed PO dicing tape for SD process through dicing tape by conducting various evaluations. In this study, we report details of the development process of novel PO base film dicing tape with the same performance as PVC base film dicing tape and successfully separated a 12 inch silicon mirror wafer into 1 mm die squares and 12 inch silicon mirror wafer with the back side protection-film into 6 mm die squares.

“Manufacturing Technology Solution of Fan-out Packaging for Heterogeneous Integration”

Abstract Invited Session on FUTURE SEMICONDUCTOR PACKAGES FOR AI HARDWARE. Outline: Introduction; Target of Advanced PKG Technology for HI; Technology Solution (1. New SAP Flow of Fan-out IC Substrate; 2. Fine L / S IC Substrate Patterning by Wafer Process; 3. Technology Strategy by PCM and TSV for AI Hardware; 4. Summary); and Acknowledgments.

Recent Advances in Underfill Materials

Abstract Invited Session on FUTURE SEMICONDUCTOR PACKAGES FOR AI HARDWARE. Outline: Applications for Advanced Packaging; Global AI Computing Hardware Total Available Market (TAM); Die partitions; Defect Density; FC-BGA Families Trends; Technical Challenges of CUF; Underfills for Advanced Packaging; Severe KOZ on MCM; Bleed Out; Formulation Technique; Concerns during penetration; Chip package interaction (CPI) Challenges; and summary.

Packaging Renaissance with Chiplets

Abstract With ever shrinking advanced CMOS nodes and evolution of systems with increasing complexity, the traditional SoC paradigm is facing extensive challenges in terms of yields and heterogeneity. The emerging industry solution to this has been to partition the SoCs into smaller units, with each unit performing a certain (though exclusive) function. This drove the birth of “chiplets”. With advent of chiplets, the traditional function of packaging as an after-thought to chip development has got a revolutionary face-lift. Packaging is now enabling interconnects to replace on-chip global interconnects. The onus now is on packaging to get the chiplets to integrate and communicate with each other such that the net performance is equivalent to or better than SoC. This has spawned a renaissance in field of semiconductor packaging, with newer multi-die packaging technologies being productized to realize newer and better interconnects. Some examples of these emerging technologies include advanced flip-chip, 2.5D, 2.1D, 3D, Wafer Level Fan-Out, and Bridge Technologies. AMD is at forefront of chiplet technologies, with extensive 7nm chiplet based product portfolio catering to the HPC market. This talk will discuss the current state of chiplet packaging technologies.