Abstract
The paper focused in addressing the silicon die chippings defect at the wafer sawing process of an extremely small semiconductor package. In-depth potential risk analysis and Pareto diagram were done to identify the top reject contributors and eventually resolve the issue. A comprehensive design of experiment (DOE) was done and validation of the solution was employed to formulate the effective corrective actions. Results revealed that die chippings were addressed by optimizing the wafer sawing process through enabling the dressing, pre-cut and step-cutting modes. Ultimately, an improvement of 95% for die chippings reduction was achieved.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
