Semiconductor Packaging Research Articles

Characterization of laser beams: theory and application in laser-assisted bonding process

The International Organization for Standardization (ISO), in collaboration with the academic community, has developed and published a comprehensive system of standards for the characterization of optical components and laser beams. Our study offers a pedagogical introduction to the theory and application of laser beam characterization in accordance with ISO 13694:2018 and ISO 11145:2018. The characterizing parameters of each ISO standard are presented, defined mathematically, and explained in detail through the use of a minimum working example. A laser beam applied to an actual industrial process [laser-assisted bonding (LAB) process in the semiconductor packaging industry] is thoroughly analyzed to help the reader understand and interpret the characterizing results. Background noise correction and unit conversion methods are also discussed. We target researchers new to the field of laser beam analysis who want the acquire background knowledge, as well as more experienced researchers who want to implement their own laser beam analysis software and propose new definitions for their specific application. Although our study deals with only two ISO standards, the methods covered in our study can be easily applied to other norms that fit the reader’s application. Our study should not be treated as a full review of the LAB process nor of the beam profiling instruments and measurement principles. These are only mentioned to enhance the reader’s learning experience.

REMOVED: Crystallinity-tailorable solvent-free hybrid adhesive films composed of epoxy, diacid, and poly(ethylene glycol) with curable and deoxidizing capabilities

The technology of curable adhesive films capable of deoxidization is still in its infancy. Herein, an eco-friendly solution lies in utilizing an epoxy binder, a diacid, and a thermoplastic matrix with low transition temperature, namely, poly(ethylene glycol) (PEG). We fabricated a specially designed hybrid adhesive film with curable and deoxidizing capabilities by harnessing and controlling acidic moieties. The deoxidizing capability of the films and the crystallinity of PEG in the cured films were further controlled by the combination of acidic concentrations and reaction times. Acidic concentrations higher than the stoichiometric ratio (1:1) between the epoxy binder and pimelic acid considerably hindered the PEG crystallinity in the cured films. This suppressed crystallinity was observed based on DSC, POM, XRD, and FTIR results. The rheological and mechanical properties were systematically examined. The fabricated hybrid adhesive films with curable deoxidizing capabilities can be useful in a myriad of applications, such as electronics and semiconductor packaging that require soldering.

Finite element analysis of moisture induced thermo-mechanical delamination of semiconductor packages considering in-situ moisture desorption during reflow process

Polymers are highly affected by moisture and temperature in terms of reliability of packaging. Especially, interface delamination between dissimilar materials with polymer is one of the major issues to the structural integrity and reliability, which is affected significantly by temperature and moisture concentration. In this paper, moisture absorption characteristics and thermo-mechanical delamination of semiconductor packages were predicted by finite element analysis considering moisture and temperature changes during the reflow process simultaneously based on a home-made user's subroutine. To implement the delamination through finite element analysis, moisture absorption experiments were conducted to evaluate hygroscopic properties (diffusivity, concentration) of the package material with different relative humidities (RH) and temperatures. In addition, adhesion strength of bi-material was evaluated by a micro-scale shear test. The measured adhesion strength of bi-material such as Epoxy molding compound (EMC)/Chip, Chip/substrate, and substrate/EMC were implemented in the user's subroutine with respect to the moisture concentration and temperature. The user's subroutine based finite element analysis code was developed to analyze the combined effect of hygroscopic and thermal deformation. As a result, interface delamination was successfully predicted considering the in-situ moisture desorption and temperature increase during the reflow process and interfacial failure strength considering the temperature and moisture concentration.

Effect of Silicon Die Condition on the Breaking Load Performance of a Dam and Fill Semiconductor Package

A semiconductor package has a silicon die on which an integrated circuit (IC) is fabricated. The die is singulated from a single wafer using processes like mechanical sawing or laser grooving. These processes have impact on the final condition of the silicon die after wafer singulation. This paper discusses a study on the effect of the die condition on the breaking load of a package with a dam and fills structure. The encapsulation material of this type of package has lower modulus when compared with the epoxy mold compound material used in most molded packages. The package breaking load was determined using 3-point bend test for two sets of packages. The first set of packages was assembled with silicon die produced using mechanical sawing. The second set was assembled with die produced using laser grooving. Results of the 3-point bend test showed that the breaking load of the package with die from mechanical sawing is higher compared with the package assembled with die from laser grooving. The study revealed that that the silicon die condition has significant effect on the robustness of the final package where the die is used.

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Reliability evaluation of ultra thin 3D-IC package under the coupling load effects of the manufacturing process and temperature cycling test

In the development of semiconductor packaging technology from planar to three-dimensional vertical integration, chip interconnection density has increased, and the distance of signal transmission has dropped to improve overall device performance. In this research, an architecture composed of through‑silicon via (TSV) and solder microbump (μbump) is utilized to assemble an ultra thin-type chip into a three-dimensional integrated circuit (3D-IC) package. To explore the influence of residual thermomechanical residual stress induced during the manufacture of the 3D-IC package on the subsequent reliability of the thermal cycling test (TCT), this study establishes a nonlinear simulation methodology for investigating the coupling effect of the manufacturing process and the TCT. The plastic and creep behaviors of the solder μbump are considered in the finite element modeling. The concerned geometric dimensions and underfill materials are also parametrically analyzed. Furthermore, the inelastic strain accumulated in the crucial SnAg solder μbump is examined. Results indicate that the residual strain in the manufacturing process causes an obvious packaging warpage and converges at the subsequent TCT stage. The creep of the solder μbump increases up to 50% in thermal cycling, thereby highlighting the importance of considering the creep model. Moreover, the parameterization of chip thickness can minimize the inelastic strain increment of the solder μbump, and the low Young's modulus of the underfill materials exerts a significant effect on the warpage of the packaging module and the stress compliance of the μbumps.

Interface mechanical behavior of gold alloy wire bonding

The connection between the internal chip and external pins of the semiconductor package and the connection between the chip play an important role in establishing the electrical connection between the chip and the outside and ensuring the input/output between the chip and the outside. It is the key to the entire subsequent packaging process. Wire bonding has a dominant position in connection methods due to its simple process, low cost, and application of a variety of packaging forms. In high-reliability fields such as military and aerospace applications, bonding wires are usually used as chip interconnect materials. The bonding wires have good electrical conductivity, thermal conductivity, and oxidation resistance, but there are some reliability problems in bonding due to the production of Au-Al compounds. In this paper, Al element is used to modify the bonding alloy wire innovatively, the mechanical properties of Au-Al and Au-Pd system bonding points and the growth and evolution of IMC are studied, and the influence of Al and Pd elements on the reliability of bonding points is evaluated.

Modeling Study on the Impact of Mold Thickness on Strip Warpage of a Molded Leadframe Package

Strip warpage is a common problem in molded leadframe packages. When warpage becomes excessive, the strip could not be processed as it would result in the strip being stuck or damaged during loading to the handling machine loader. This study focuses on the impact of mold cap thickness on strip warpage of a molded Quad Flat No Lead (QFN) package to provide guidance in reducing the strip warpage to an acceptable level. Different mold thickness values were considered in the modeling using finite element analysis (FEA). Results showed that there is an optimum mold thickness, which is around 1.0 mm for 0.20 mm leadframe thickness and 0.65 mm for 0.125 mm leadframe thickness, that gives the lowest warpage in the case considered. The optimum mold cap thickness is lower for thinner leadframe. At mold thickness lower than the optimum value, warpage is in “frowning” mode and increases as the package gets thinner and this agrees with actual observations. This study shows that mold cap thickness has significant impact on molded strip warpage and could be assessed using FEA. Therefore, controlling the mold cap thickness could now be considered an option to reduce strip warpage in molded semiconductor packages as supported by modeling.

Study of the Impact of Curing Condition on Flexural Strength of a Very Thin Semiconductor Package

Thinner semiconductor package is becoming popular especially in consumer electronics applications. As package becomes thinner, it is more vulnerable to package crack when subjected to external load. It is important to ensure that the package is strong enough to resist package cracking. This paper presents the study of package flexural strength under different epoxy mold compound curing condition. A 3-point bend test was done to characterize the breaking strength of the package that was subjected to post-mold curing. It was then compared to the strength of the package not subjected to post-mold curing (PMC). Results of the bend testing showed that the package flexural strength is much lower when the package is not subjected to post-mold curing. This study demonstrates that the measurement of flexural strength can be used to determine if the package has undergone post-mold curing or not. Performing the right post-mold curing of the thin molded package is required to ensure higher flexural strength.

Formation mechanism of Cu/Cu3Sn–Cu/Cu interconnections based on solder-filled microporous copper as interlayer via a current-assisted thermal compression bonding

In this study, a Cu/Cu3Sn–Cu/Cu interconnection can be achieved based on solder-filled microporous copper (MPC) as interlayer via a current-assisted thermal compression bonding. The high-temperature soldering connection materials can be used in the third-generation semiconductor packaging, so as to meet the promising application in high-temperature power device packaging. The influence of auxiliary current on the microstructure evolution of Cu–Sn IMCs and its formation mechanism were studied. Experiments show that the action of Joule heat coupled with the electron wind significantly enhanced the interfacial reaction at the Cu/Sn metallization interface. The microstructure of Cu6Sn5 changed from scallop-like into columnar due to constitutional supercooling, and the dispersion distribution of Cu6Sn5 also changed. The growth constitutive equations of Cu3Sn in bondlines were established under current-assisted thermal compression bonding process.

Microstructural characterization of alloyed palladium coated copper wire under high temperature

Palladium coated copper (PCC) wire has been increasingly used in the semiconductor package in the last 10 years, especially in consumer products as a low-cost alternative to gold (Au) bonding wire. However, the PCC wire is still not widely used in the automotive industry due to the reliability limitations under a high temperature condition. In order to improve the long term reliability of PCC wire under a high temperature condition, new additive elements in the Cu core have been considered. In this paper, we investigate the role of additive elements in PCC wire and their effect on corrosion resistance under high temperature conditions. Pd and platinum (Pt) are examined as additive elements. Additive Pd and Pt in PCC wire become a cause of degradation for the stitch bond reliability under the high temperature condition due to the different degradation microstructure from conventional PCC wire.

Predicting Silicon Die Breaking Force in Semiconductor Package Assembly through Mechanical Simulation

Die crack is a common problem in the semiconductor industry and being able to predict the breaking force at a given loading condition could help prevent such crack problem. This paper presents the use of mechanical simulation in predicting the force at which the silicon die breaks in semiconductor package assembly process. A computer simulation with finite element analysis (FEA) technique was used. The applied force or displacement in a die bending simulation with 3 mm, 4 mm and 15 mm support span was varied until the resulting maximum principal stress of the die becomes equal to its fracture strength. Results revealed that the breaking force for the 70 µm die with 6 mm width is around 5 N for the 3 mm support span and only around 1 N for the 15 mm support span. With the good agreement between modeling and actual results, the study showed that mechanical simulation is an effective approach in predicting die breaking force and can be used to simulate different mechanical loads in the package assembly where possible die crack could happen and be avoided. This is a fast and cost-effective way of assessing risk of die crack and obtaining package assembly process parameters and specifications that are safe to the silicon die.

Impact Modifiers and Compatibilizers for Versatile Epoxy-Based Adhesive Films with Curing and Deoxidizing Capabilities.

Epoxy resins with acidic compounds feature adhesion, robustness, and deoxidizing ability. In this study, hybrid adhesive films with deoxidizing and curing capabilities for semiconductor packaging were fabricated. The compatibilizing effects and mechanical properties were chiefly investigated by using various additive binders (thermoplastic amorphous polymers) and compatibilizing agents. The curing, deoxidizing, thermal, and rheological properties were systematically investigated. For uniform film formation and maximizing deoxidizing curable abilities, a thermoplastic–thermoset mixture containing a phenyl and carboxylic acid-based additive (benzoic acid), and a polycarbonate was chosen as the model adhesive film. Without either a phenyl or an acidic group in the compatibilizing agent, deoxidizing and compatibilizing effects were not achieved. The manufactured hybrid adhesive film can be effectively used, especially for electronic devices that require deoxidization and adhesion.

GE SiC Semiconductor Device Operation at Extreme Temperatures

Abstract GE Research has been working on the design, packaging, and testing of SiC Power semiconductors devices at junction temperatures up to 500°C for the past 5 years. Intrinsically, SiC power devices are able to endure and operate reliably at harsh environments. Limiting factors to packaged devices’ operation at high temperature are the contact metallization and packaging. While testing bare die power devices, probe contact resistance was found to be an issue for resistance measurements at very high temperatures. On the backside contact, traditional die attach solders have operational temperature limits. Using insulated metal substrates, sintered die attach, and wedge bond interconnect, GE Research tested its power devices up to 500°C junction temperature. GE Research also demonstrated various junction termination dielectric stackups which can block up to 1000V at 500°C junction and show improvements over traditional organic dielectric options (e.g. Epoxy, Silicone, Polyimide).

Nozzleless Acoustic Droplet Ejector With Electrically Tunable Droplet Size for Picking and Placing Semiconductor Chips

This paper presents a microfabricated nozzleless acoustic droplet ejector with electrically tunable droplet size as a new tool for on-demand picking and placing semiconductor chips for semiconductor packaging. The ejector is based on a 2-mm-thick lead zirconate titanate (PZT) sheet with a planar annular-ring air-cavity acoustic Fresnel lens on top. When driven with sinusoidal pulsed voltage signals of 1.16 MHz, the ejector generates focused ultrasound with 1-mm focal diameter and 5-mm focal depth at 22 mm focal length in sodium polytungstate (SPT) solution. A finite-element-method (FEM) simulation model calculating the acoustic-field-induced fluid motion during the droplet ejection process has been developed, and verified by experiments, in which the device ejects SPT droplets whose diameter is from 850 to 2, 490 μm, controlled by the driving pulse width and voltage. The ejected droplets are able to carry 400- μm-thick square silicon chips with side length from 700 to 3, 100 μm. A polyester channel-embedded guiding cover for semi-automatic loading of silicon chips to the ejection site is designed to avoid manual placement of the silicon chips. With the proof-of-concept system, we demonstrate ejecting silicon chips out of SPT surface onto a nearby paper, assembling them into arrays with good repeatability. [2020-0337].

Laminar Metal Foam: A Soft and Highly Thermally Conductive Thermal Interface Material with a Reliable Joint for Semiconductor Packaging.

Future electronic packaging technology requires semiconductor chips having a larger size and higher power for advanced applications, e.g., new energy conversion systems, electric vehicles, and data center servers, yet traditional thermal interface materials (TIMs) with a high thermal conductivity are generally stiff materials with weak joints, which cause the accumulated thermal stress to concentrate at the chip corners, leading to cracking and popcorn problems. To address such a critical challenge, herein for the first time we report a low-cost and high-performance porous copper (Cu)-indium (In) laminar structure as TIM, which can provide a superior thermal conductivity (50 W m-1 K-1) comparable to indium, yet the Young's modulus (1.0 GPa) is an order of magnitude lower than indium, which is a state-of-the-art value. Additionally, the In-based intermetallic compound (IMC) joints enable more robust mechanical interconnection above the melting point of pure indium, providing better high-temperature performance. The discontinuous IMCs spread the global interfacial thermal stress into numerous isolated local areas, ensuring a reliable joint to resist thermal-mechanical fatigue. In the silicon-TIM-copper package testing vehicles with a large die size (1 × 1 square inch), this structure shows excellent thermal management ability and superior reliability, compared with classical indium and classic commercial silver pastes.

Study on the Impact of Lead Sidewall Solder Coverage and Corner Lead Size on Joint Reliability

Solder joint reliability is very important to ensure that an integrated circuit (IC) semiconductor package is functional within its intended life span as the solder joint establishes electrical connection between the IC and the printed circuit board (PCB). Solder fatigue failure or crack under thermal cycling is one of the common problems with board-mounted packages. There are several factors or package characteristics that have impact on solder fatigue life like package size and material properties of the package components. This paper presents a thermo-mechanical modeling of a leadframe-based semiconductor package to study the impact of lead sidewall solder coverage and corner lead size on the solder joint reliability. Finite element analysis (FEA) technique was used to calculate the solder life considering 50% and 100% package lead sidewall solder coverage as well as smaller and larger critical corner leads of the package. The results of the analysis showed that higher lead sidewall solder coverage and larger lead could significantly increase solder life. Therefore, ensuring lead sidewall solder wettability to have higher solder coverage is beneficial. The study also reveals that packages with side wettable flanks are not only enabling high speed automated optical inspection required for the automotive industry, but they are also providing improved solder joint reliability.

Physics of Failure (PoF) Based Lifetime Prediction of Power Electronics at the Printed Circuit Board Level

This paper presents the use of physics of failure (PoF) methodology to infer fast and accurate lifetime predictions for power electronics at the printed circuit board (PCB) level in early design stages. It is shown that the ability to accurately model silicon–metal layers, semiconductor packaging, printed circuit boards (PCBs), and assemblies allows, for instance, the prediction of solder fatigue failure due to thermal, mechanical, and manufacturing conditions. The technique allows a life-cycle prognosis of the PCB, taking into account the environmental stresses it will encounter during the period of operation. Primarily, it involves converting an electronic computer aided design (eCAD) circuit layout into computational fluid dynamic (CFD) and finite element analysis (FEA) models with accurate geometries. From this, stressors, such as thermal cycling, mechanical shock, natural frequency, and harmonic and random vibrations, are applied to understand PCB degradation, and semiconductor and capacitor wear, and accordingly provide a method for high-fidelity power PCB modelling, which can be subsequently used to facilitate virtual testing and digital twinning for aircraft systems and sub-systems.

Enhanced Wirebonding Technique on QFN Device with Critical Die Reference

Wirebonding is one of the most challenging assembly manufacturing processes in semiconductor packaging industry. This paper discussed the wirebonding challenge and the solution to mitigate misplaced ball issues and prevent pattern recognition alignment errors. Parameter optimization particularly on wirebond looping was done to ensure that the silicon die’s L-fiducial is visible and not obstructed by the wires, which is the operator point or die reference of the unit during wirebonding setup. Ultimately, the optimized wirebonding parameter prevented the pattern recognition alignment error and misplaced ball issues during the lot process. For future works, the configuration and technique could be applied on packages with the similar situation.

Investigation on Die Crack in a Stacked Die Package Using Finite Element Analysis

Die crack is one of the problems in stacked die semiconductor packages. As silicon dies become thinner in such packages due to miniaturization requirement, the tendency to have die crack increases. This study presents the investigation done on a die crack issue in a stacked die package using finite element analysis (FEA). The die stress induced during the package assembly processes from die attach to package strip reflow was analyzed and compared with the actual die crack failure in terms of the location of maximum die stress at unit level as well as strip level. Stresses in the die due to coefficient of thermal expansion (CTE) mismatch of the package component materials and mechanical bending of the package in strip format were taken into consideration. Comparison of the die stress with actual die crack pointed to strip bending as the cause of the problem and not CTE mismatch. It was found that the die crack was not due to the thermal processes involved during package assembly. This study showed that analyzing die stress using FEA could help identify the root cause of a die crack problem during the stacked die package assembly and manufacturing as crack occurs at locations of maximum stress. The die crack mechanism can also be understood through FEA simulation and such understanding is very important in coming up with robust solution.