Semiconductor Packaging Research Articles

I4.0 Pilot Project on a Semiconductor Industry: Implementation and Lessons Learned.

Industry 4.0 considers the combinations of Internet of Things, computing and communication infrastructure, sensors, and artificial intelligence (AI) to provide predictive maintenance and process optimization. These benefits are very relevant to the semiconductor industry, where high reliability and low operating costs are critical for a business’ success. Analyzing the state-of-the-art of the projects that present the implementation of the fourth industrial revolution in semiconductor companies, we noticed mainly two branches of initiatives: (i) articles that explain the final achievements, not detailing how they were assembled and structured; (ii) articles that detail a part of the industry ecosystem, for example, approaching only the communication system or AI algorithms. In this context, this article proposes an I4.0 Pilot as a compilation of lessons learned during an end-to-end development of a reference design applied to a semiconductor packaging and test company. We explore the requirements of clean rooms and information related to sensors and data acquisition boards, in addition to performance details and configurations pertaining to visualization tools and warning notifications. The main contribution appears in presenting the advantages of adopting flexible decisions in the pilot to enable the best characteristics for a final expandable solution. Our final idea is to emphasize the importance of having a pilot project without significant expenses, presenting the reader with the acquired knowledge, and how they can benefit from it.

A Study of Thermal Resistance for Surface Mount Type Power Semiconductor Packages

A Study of Thermal Resistance for Surface Mount Type Power Semiconductor Packages

High-accuracy simultaneous measurement of surface profile and film thickness using line-field white-light dispersive interferometer

White-light dispersive interferometry (WLDI) is an instantaneous, high-resolution optical metrological technique for measuring precise and complicated surfaces. This method enables nondestructive inspection of transparent-film-structure devices that are widely used in semiconductor packaging. We propose in this paper to use a home-built WLDI system with line-by-line spectral calibration, phase-shifting algorithm, and single-wave-number method for high-accuracy, simultaneous measurements of surface profiles and film thickness. By calibrating the relationship between wave-number and pixel position on each line of a two-dimensional detector, the line-by-line calibration method improves the measurement accuracy by correcting the spectral distortion caused by the optical system. Moreover, the spectral signal phase is obtained by the phase-shifting algorithm instead of by the Fourier transform method. The single-wave-number method is applied to the computation process by introducing the fringe order, and the measurement result indicates that it enhances the system immunity to environmental noise. A 1.806-µm-high standard step and a 1052.2-nm-thick standard film are measured to verify the system performance and show that the system is highly accurate and reliable.

Life cycle impact assessment of semiconductor packaging technologies with emphasis on ball grid array

Environmental impact assessment studies have completely and rapidly focused on the shift from economic to environmental competitiveness in semiconductor packaging industries under the trend of small size and diverse semiconductor products. This study has two main objectives, namely, (1) to adopt traditional life cycle impact assessment (LCIA) for investigating the environmental damage of three packaging technologies, namely, ball grid array (BGA), flip chip (FC), and lead frame (LF). Two commonly used materials in 2017, namely, gold and copper wires, were analyzed. The functional unit was defined on the basis of the packaging volume (1 mm3); (2) to identify influential parameters for developing two parametric LCIA equations for the BGA. Results show that the semiconductor back-end industry should gradually replace gold wires with copper wires without affecting the function of products and should promote the low impact packaging technology (LF) while satisfying the customer’s demands. Tree influential parameters (packaging volume, wire mass, and lead counts) of LCIA are identified by regression analysis, and the lead count can be considered a worthwhile alternative parameter for allocation and establishing the parametric tool when the packaging volume of the product is unavailable. The parametric tool can reduce the time cost of collecting LCI data and avoid the analysis errors and uncertainty caused by the distribution. The research can serve as a guide for the PCRs (LCA-PCR) of the semiconductor industry for suitable alternative allocation principles and functional units.

Optimization of process parameters of anodic aluminium oxide using an orthogonal array technique for thermal management applications

The semiconductor packaging field is evolving rapidly due to strong competition in customer demands for increased functionality and performance, further miniaturization, heightened reliability and lower costs. The lifetime reliability and sequential performance of solid-state products are mainly based on the device junction temperature (Tj). The main concerns of efficient thermal management in heat source-based electronic packages are controlling and reducing the device junction temperature and total thermal resistance (Rth). The optimization of process parameters to develop an anodic aluminium oxide nanopore (AAO-np) structure on an Al5052 alloy substrate using an electrochemical process (two-step anodization) is proposed based on the Taguchi orthogonal array (L9). The four major parameters are the electrolyte, anodization time, bath temperature, and applied voltage, which are varied at three different levels. This experiments aim to finalize suitable process parameters and their levels towards optimum Rth and Tj. The morphology of the step-wise preparation of AAO-np structure is discussed for the optimized conditions of 0.3 M oxalic acid, a 3 h anodization time, a 30 V applied voltage, and a bath at room temperature. The resulting AAO-np structure has a pore diameter of 40 to 55 nm and a height of 6 to 7 μm. This formation significantly reduces Rth by 24.58% and Tj by 24.66% for the electronic package compared to a bare Al substrate.

Exploiting Distinct Thermal Response Properties for Power Semiconductor Module Health Monitoring

This article develops the techniques for actively tracking response shifts, induced by thermal–mechanical degradation over components lifetimes’, in spatiotemporal thermal response dynamics. The methodology considers both boundary (e.g., cooling) and internal (e.g., voiding) sources of degradation, and it is considered in the context of power semiconductor devices and packages, including power modules. This article quantifies the transient thermal response sensitivity to degradation using electrothermal impedances viewed with key frequency response function (FRF) metrics over wide dynamic ranges. A developed sensitivity analysis is applied using models and experimental evaluation to relate temperature sensing spatial location, harmonic content of semiconductor device losses, and source of degradation in terms of normalized FRFs that are rapidly interpreted. Complementary loss model parameter sensitivity analysis reveals the advantages in tracking variation in thermal FRF phase delay, rather than amplitude. Finally, to complement pure-FRF approaches for sensing degradation, which use nonparametric data, a method for directly estimating degradation-sensitive physical parameters, in real time, is developed. Experiments demonstrate the automatic estimation of a thermal resistance parameter.

Resolution of Damaged Metallization on Highly Complex Semiconductor Device

The paper focused on the resolution of damaged metallization during assembly process that lead to gross open-short (O/S) rejections during functional testing of a highly complex semiconductor package. Numerous batches were put on hold due to not meeting the specification assigned for the short contact test. Design of experiments (DOE) on assembly processes were conducted and eventually identified the reject as an electrostatic discharge (ESD) related failure. Corrective actions and ESD controls significantly reduced the occurrence of damaged metallization with around 85% reduction.

Semiconductor Package Design Solution for Addressing High-Density Configuration

The direction for integrated circuit (IC) packaging is getting smaller yet with increasing unit performance. In this case substrate-based technology became limited to miniaturization and downsizing direction. In this paper, a specialized design of IC is presented and discussed through augmentation of routing channels at the backside of the silicon die to eliminate the substrate application in the package. Routed channels are fabricated using plating or immersion process that are electrically connected to the bonding pads through conductive via within the silicon material. By eliminating the substrate re-distribution layers (RDL), a package is expected to decrease by 20 – 40% from its designed dimension.

Defect Characterization of Advanced Packages using Novel Phase and Dark Field X-Ray Imaging

Abstract Modified Talbot X-ray interferometry provides three contrast modes simultaneously: absorption, phase, and dark field/scattering. This article describes the powerful new imaging technique and shows how it is used to characterize various types of defects in advanced semiconductor packages.

An improved measure of quality loss for notching processes

AbstractNowadays, electronic products are progressively becoming thinner, lighter, and more convenient for people to use. Printed circuit boards, and especially integrated circuit (IC) substrates, are among the essential component of these products. The IC substrate not only protects circuits, fixes lines, and conducts heat, but is also the critical component that provides signal connectivity between the chip, the printed circuit boards, and other crucial parts during the packaging process. The process capability index Cpm is commonly used to assess the product quality loss for decision making in modern semiconductor packaging manufacturing. For high‐definition products, packaging processes often have very strict quality requirements and thus the quality inspection procedure is time‐consuming and complicated. Therefore, because of the limitation of manpower and capacity of the inspection instruments, the collected sample for quality assessment may be with small to moderate sample sizes. In this paper, we introduce an unbiased estimator for Cpm and provide a step‐by‐step parametric bootstrap procedure for obtaining a composite lower confidence bound on Cpm. To compare with the approaches discussed in the literature, numerical simulations are conducted under various process parameter settings. The results show that for small to moderate sample sizes, the proposed method applying the unbiased estimator has more accurate coverage rates than the existing methods. At the end of this paper, an application of quality loss assessment in notching processes is demonstrated.

Thermomechanical stress in GaN‐LEDs soldered onto Cu substrates studied using finite element method and Raman spectroscopy

AbstractLocal thermomechanical stress can cause failures in semiconductor packages during long‐time operation under harsh environmental conditions. This study helps to explain the packaging‐induced stress in blue GaN‐LEDs soldered onto copper substrates using AuSn alloy as lead‐free interconnect material. Based on the finite element method, a virtual prototype is developed to simulate the thermomechanical behavior and stress in the LED and in the complete LED/AuSn/Cu assembly considering plastic and viscoplastic strain. The investigations were performed by varying the temperature between −50°C and 180°C. To validate the model, the simulation results are compared to experimental data collected with Raman spectroscopy. Studies of the phonon mode of GaN semiconductor are elaborated to understand the induced thermomechanical stress. The model enables evaluation of the stress in the interfaces of the assembly, which otherwise cannot be accessed by measurements. It serves to predict how assemblies would perform, before committing resources to build a physical prototype.

Effect of Backgrinding Tape Lamination on Die Alignment

The continuing growth and development on semiconductor package miniaturization have become a particular interest and focus semiconductor industry. The importance of thinner packages also demands a thinner vertical structure of the integrated circuit (IC) design with silicon die or the wafer playing essential role in package thinning. As the wafer goes thinner, problems may occur in the wafer preparation or pre-assembly. With the introduction of new wafer preparation technologies such as dicing before grinding and laser die attach film (DAF) cut, technical challenges were inevitable. The paper focused on the effect of backgrinding tape lamination on die alignment. Tensionless lamination helped eliminate the horizontal pressure applied into the tape thus mitigating the die mis-alignment problem. For future works, the configuration could be applied on wafers with similar technology and/or application.

Ejectorless Method for Die Attach Pick Up for Cracking Improvement on Thin High-Aspect Ratio Die

<p>The demand for producing small, thin, and light electronic devices is increasing. As a result, the design and assembly of electronic packaging technology have been developed. To meet the ever-increasing technology requirements, the critical process in the semiconductor packaging include wafer back grinding, sawing, and die attach. Given that the die thickness is lower than the previous ones, the risk of die cracking failures, which can lead to device malfunction, becomes high. In the die attach process, the ejector pin has an effect during the pick and place processes. Such impact may result in microdented mark or microcrack underneath the die, which becomes the weakened point throughout the entire process. In this study, an ejectorless system for the die pick and place during the die attach process has been designed and evaluated. The methodology of using ejector pin is replaced by heated static pillar inside cavity for die platform before being picked up. Vacuum is used to stabilize the die, and heat is applied to soften the sawing tape and weaken the adhesion of the die to the sawing tape. Results show that the critical issues of die crack for thin high aspect ratio die are resolved by using the proposed method for the die pick during the die attach process. In conclusion, the semiconductor packaging advances the pick-up technology solution for the challenging material, which is needed for the current miniaturization market trend and demand. <br /><br /></p>

Finite element analysis on the factors affecting die crack propagation in BGA under thermo-mechanical loading

Ball grid array (BGA) is one of the most innovative semiconductor packaging technologies which is capable of high input-output capacities while addressing handling and coplanarity compared with other packages. However, the BGA package is subjected to thermo-mechanical load which makes it susceptible to quality and reliability issues such as die crack. The occurrence of die crack is difficult to monitor as it is considered as an internal package issue and can be catastrophic to the electronic device which may lead to its failure. This study aims to investigate the various factors affecting die crack propagation using finite element analysis (FEA) model under thermo-mechanical loads. The energy release rate in the silicon die was used to quantify the propagation of die crack in the BGA package. The influence of the various factors on the propagation of die crack was determined through a design of experiment approach consisting of the definitive screening for initial factor screening, and response surface method through the central composite design. The results have shown that the die thickness, the glass transition temperature, the in-plane CTE of the substrate, and the initial crack length are the factors significantly affecting the die crack propagation in a BGA package. Moreover, at critical parameter conditions, the results have identified a critical crack length of 0.02236 mm. The study is aimed to benefit the research, design, development, assembly, and material engineers in the semiconductor industry providing insight to the die crack propagation of a BGA package.

Bond Line Thickness Characterization for QFN Package Robustness

The paper focused on the evaluation of quad-flat no-leads (QFN) semiconductor package with small silicon die on different machine platforms to achieve a higher bond line thickness (BLT) of greater than 30 µm. The characterization or evaluation was narrowed down into two main diebonding machines with the objective of attaining a higher BLT for small die. High BLT capability is desired to generate clearance for the shrinkage of the glue, henceforth mitigating the glue voids. Diebond Machine 2 was able to achieve the target BLT with 30.89 µm average compared to 18.25 µm for Machine 1. Moreover, the target BLT range could only be achieved in Machine 2 only. For future works, the machine and configuration could be used for devices with comparable requirement.

From active phased array antenna to antenna array microsystem in post-Moore era

In this review, we analyze and study the characteristics, current status, developing trend, and bottleneck technologies of active phased array antennas by highlighting the high-resolution earth observation microwave imaging radar demands for highly-efficient, low-profile, and lightweight antennas. We present the concept and contents of antenna array microsystem and several leading-edge technology issues based on predications of integrated circuits (ICs) development in the post Moore era. The multi-physics coupling model under the micro-nano scale involved in antenna array microsystem, critical technologies such as microwave semiconductor ICs, hybrid/heterogeneous integration, packaging and functional materials, and their solutions are described and explored. This study prospects the antenna array microsystem potentially applied in the next generation of microwave imaging radar.

Microdrilling Machinability of Organic Material for Semiconductor Packaging by 248 nm Excimer Laser

Microdrilling Machinability of Organic Material for Semiconductor Packaging by 248 nm Excimer Laser

Minimizing Temperature Nonuniformity by Optimal Arrangement of Hotspots in Vertically Stacked Three-Dimensional Integrated Circuits

Abstract The semiconductor packaging technologies have seen its growth from multichip module (MCM), system in package (SiP), system on chip (SoC) to the heterogeneous integration of the MCM. Thermal management of multichip vertically integrated systems poses additional constraints and limitations beyond those for single chip modules. Three-dimensional-integrated circuits (3D ICs) technology is a potential approach for next-generation semiconductor packaging technologies. A 3D IC is formed by vertical interconnection of multiple substrates containing active devices which offer reduced die footprint and interconnect length. This paper discusses the optimal arrangement of two hotspots on each layer of a two-die stacked 3D IC. An analytical heat transfer model for prediction of three-dimensional temperature field of a 3D IC based on the solution of governing energy equations has been developed and used for this study. The model is subject to adiabatic boundary conditions at the walls except for the bottom wall which is subject to convective boundary condition. A feed-forward back propagation artificial neural network (ANN) is employed for obtaining the functional relationship between the location of the hotspots and the objectives. Genetic algorithm is employed for solving two nonconflicting objective functions subject to set of constraints. The first objective aims to minimize the maximum temperature on both layers, and the second objective aims to achieve temperature uniformity in the layers. The results of the optimization study are expected to provide recommendations on the design guidelines for arranging hotspots on vertically stacked substrates.

Advanced Semiconductor Design through Specialized Printable Conductive Layer

Semiconductor package miniaturization and thinning have become of particular interest among semiconductor manufacturing industries, with each manufacturing company having specific approach and technical directions in providing unique solutions in their products. The paper provides a specialized design of manufacturing flow for semiconductor device through advanced fabrication method using stencil printing. The advanced process would significantly reduce the carrier thickness for the overall package height configuration of the device. The implementation of the specialized design and process would mitigate common assembly barriers and defects related in producing thin devices, hence, enabling cost-saving realization and manufacturing solution to package thinning and miniaturization with multiple input/output (I/O) requirements.

Automatic Optical Inspection System with Telecentric Optics and Phase-measuring Profilometry for Highly Accurate Localization of Electronic Packages

Typical visual placement inspection systems in semiconductor or electronics manufacturing industries use only highly-magnified two-dimensional imaging with controlled illumination for high accuracy. However, current semiconductor packaging technology needs more precise manufacturing processes for highly integrated semiconductor packages, in which high-precision alignment between the semiconductor die and the matched substrate is indispensable for successful electronic interconnection. To solve this problem, an advanced visual placement inspection system for 3D stacking of electronic components is proposed; it utilizes 3D profilometry and 2D telecentric optics. In addition to the introduction of the proposed system, the system calibration algorithms and the information processing algorithms for accurate positioning of the semiconductor die, as well as the implemented inspection system are described in detail. To verify the system performance, a series of real experiments on newly developed flip-chip packages for high-performance computing were performed, and the results are analyzed and discussed.