Semiconductor Packaging Research Articles

Semiconductor Package Challenges toward 10 Years Later

Semiconductor Package Challenges toward 10 Years Later

Microstructure and thermophysical properties of graphite foam/Sn-Bi alloy composites for use as a thermal sink for electronics

Two mesophase pitch-based graphite foams with densities of 0.62±0.01 (GF1) and 0.84±0.01 g/cm3 (GF2) were prepared by foaming the pitch in an autoclave at 723 K, 6.0 MPa and 763 K, 13.4 MPa, respectively, followed by carbonization at 1273 K for 2 h and graphitization at 2973 K for 0.5 h. The GFs were infiltrated by a Sn-Bi liquid to prepare GF/Sn-Bi alloy composites for use as thermal sinks for electronics. The microstructures and thermophysical properties of the composites were investigated. Results indicated that GF1 had a larger cells and thinner cell walls than GF2. The Sn-Bi liquid was well infiltrated into cells of the GFs, resulting in composites with densities of 5.60±0.01 and 3.83±0.01 g/cm3 for GF1 and GF2, respectively. The thermal diffusivity and coefficient of thermal expansion (CTE) of the GF1/Sn-Bi composite were 51.6±2 mm2/s and 16.6±0.02 ppm/K, respectively. The corresponding values for the GF2/Sn-Bi were 163.1±3 mm2/s and 8.08±0.02 ppm/K. The GF2/Sn-Bi composite had a high thermal diffusivity and a low CTE value matching that of semiconductor chips and packaging materials.

Next Generation Photosensitive Dielectric Materials for Advanced Packaging Applications

Hitachi Chemical DuPont MicroSystems (HDMS) is a supplier of photosensitive negative-tone polyimides (PI) and positive-tone poly(benzoxazole)s (PBO) for use as protection layers in semiconductor ICs or as dielectrics for re-distribution layers in Fan-in or Fan-out wafer level packages. These materials offer an easy manufacturing process as well as ensuring high reliability in semiconductor packages. Recently, design rules and structures for next generation packages are advancing in order to achieve higher end multi-functionality. In accordance with this trend, next generation PIs and PBOs need to be developed to address new challenges that include lithographic properties, in-process compatibility and end-use properties and, in this paper, the latest material sets developed by HDMS will be introduced for advanced packaging applications. The 1st material set is a low stress photosensitive PI designed especially as a protection layer in advanced process node semiconductor ICs where warpage reduction and better protection capability for fragile low-k layers are needed. The 2nd and 3rd material sets are designed as low temperature curable photosensitive PI and PBO for use as dielectrics in Fan-out wafer level package to provide good applicability with future device designs as well as high package reliability by improving resolution, cured film properties, adhesion, insulation reliability, and others.

Laser Based Direct Exposure to Photo Materials Used in Advanced Semiconductor Packaging

Laser Based Direct Exposure to Photo Materials Used in Advanced Semiconductor Packaging

Crosslinkable deoxidizing hybrid adhesive of epoxy–diacid for electrical interconnections in semiconductor packaging

AbstractFor electrical interconnections in semiconductor packaging, epoxy‐based pastes have recently attracted considerable interest due to their excellent adhesion to various substrates and their reasonable electrical and mechanical properties, especially when combined with deoxidizing agents (to remove metallic oxides). Here, epoxy–diacid‐based hybrid pastes were examined to achieve a deoxidizing capability for eliminating Sn‐based solder oxides and adhesion between microchip and substrate as a one‐step process. Onset, exothermic peak and end temperatures of the reaction between epoxy and diacids were systematically probed using DSC, rheometry and Fourier transform infrared (FTIR) spectroscopy. The last moment of the adhesive reaction during heating substantially enhanced the thermal and mechanical properties of the epoxy–diacid adhesive despite the absence of exothermic enthalpy detected by DSC. The glass transition temperature (Tg) and Young's modulus gradually decreased as a function of aliphatic chain length of diacids except when the length was extremely short and voids were produced. Soldering (wetting) and deoxidizing capabilities of the hybrid adhesive were observed via optical microscopy and FTIR. The correlation between the reaction, Tg, conversion and viscosity was also investigated. Lastly, complete wetting and electrical interconnection with good mechanical robustness were achieved for a commercial chip/substrate set by flip‐chip bonding. © 2018 Society of Chemical Industry

Preparation and curing chemistry of ultra-low CTE epoxy composite based on the newly-designed triethoxysilyl-functionalized ortho-cresol novolac epoxy

For the design of the semiconductor packaging material, one of the most important challenges is to overcome the higher thermal expansion property of ‘organic’ epoxy composite than that of the ‘inorganic’ IC chip. Therefore, in order to prepare the epoxy composite with the ultra-low coefficient of thermal expansion (CTE), the new material class of epoxy, i.e., alkoxysilyl-functionalized novolac epoxy (Si(OEt)3-EOCN) was synthesized using the ortho-cresol novolac epoxy (EOCN) as a starting material. The new epoxy composite with the 85wt% of silica showed the CTE1 (at T < Tg) of 8 ppm/°C and CTE2 (at T > Tg) of 11 ppm/°C. Note that before alkoxysilyl-modification, the CTE1 and CTE 2 of the EOCN composite were 13 ppm/°C and 44 ppm/°C, respectively. In addition, the alkoxysilyl-functionalized epoxy was observed to show the unique curing chemistry due to the participation of alkoxysilyl group in epoxy curing reaction. In order to understand the chemistry of alkoxysilyl-functionalized epoxy, the reaction mechanism was studied using the model compounds.

Synchronous curable deoxidizing capability of epoxy–anhydride adhesive: Deoxidation quantification via spectroscopic analysis

ABSTRACTThermoset resins have been extensively utilized as an adhesive for electronic devices. In particular, semiconductor packaging materials between chips/substrates require electrical interconnections by using deoxidizing agents along with thermoset adhesives. In this study, a facile combination of hydroxyl‐functionalized epoxy and cyclohexane‐structured cyclic anhydrides produced curable acidic moieties, thereby allowing synchronous deoxidizing and curing without the use of a deoxidizing agent. By contrast, unitary cyclic anhydrides rarely presented acidic moieties, probably due to their rapid networkable reactivity caused by structural flexibility once opened, which was detected and quantified by spectroscopic analyses. This binary system in the absence of additional deoxidizing agents achieved the complete wetting of common Sn‐based solders via chip bonding systems due to the generated acidic moieties. The binary mixture also showed an increased glass transition temperature of 110 °C and enhanced Young's modulus of 1.6 GPa, relative to the ternary mixture (85 °C and 0.8 GPa) comprising a deoxidizing agent. This discovery is beneficial in terms of the simplification of composition design and mechanical robustness of solderable adhesives. Quantification via spectroscopic studies can also help anticipate the deoxidizing capability of binary and ternary systems at different temperatures for various bondable and solderable applications. © 2018 Wiley Periodicals, Inc. J. Appl. Polym. Sci. 2018, 135, 46639.

Investigation of Multiple Heat Source Effects in Lock-In Thermography Applications in Semiconductor Packages

Three-dimensional (3-D) packages have become a technology integrator for multiple functional devices into one component as a cost-effective way to enable Moore’s law for continuous scale-down. There are new challenges arising from the 3-D packages for fault isolation because of continued miniaturization and added complexity in the $z$ -direction of advanced IC devices, which require the development of more capable fault isolation tools and techniques for better accuracy, resolution, and sensitivity. Lock-in thermography is a powerful noncontact and nondestructive investigating technique that has recently become widely adopted in the semiconductor industry because of its sensitivity and quick time to data. As more components are integrated into 3-D packages, there are more active devices and routing becomes very complex. It is very common that multiple defects or heat sources can exist at the same time in a single package. These multiple heat sources interact with each other and affect defect depth accuracy to a very large extent. This paper presents a fundamental analysis to understand the interaction between multiple defects and its effect on the accuracy of defect depth estimation. Furthermore, this paper also presents real test cases to further the understanding and confidence in the proposed correlations. The learnings and techniques discussed in this paper can lead to industry-wide tool and technical developments, and benefit the failure analysis and 3-D package development community.

3-D X-Ray Imaging With Nanometer Resolution for Advanced Semiconductor Packaging FA

As the complexity and interconnect density of advanced semiconductor packages increase, failure analysis and root cause determination are also facing new challenges and higher requirements. The 3-D X-ray microscopy, enabling nondestructive defect imaging and enhanced navigation for failure analysis, is considered a key method to fulfill these requirements. This technique results in a short time to result and high success failure analysis yield. After a short introduction into the basic principles of laboratory-based X-ray tomography, two different approaches of X-ray investigations are discussed. The author demonstrates the capabilities of the individual techniques and gives an outlook into future failure analysis opportunities. This includes the recently developed application using 3-D X-ray imaging for back-end-of-line and chip-package-interaction features.

Direct Single Impinging Jet Cooling of a &lt;sc&gt;mosfet&lt;/sc&gt; Power Electronic Module

This paper presents an approach of direct liquid jet impingement cooling of a typical mosfet power module. A single micro water jet was installed for cooling the upper surface of a mosfet semiconductor package. In contrast to standard cooling methods, this approach focuses on hot spot removal omitting any kind of heat spreading device. The cooling chamber was directly soldered to the mosfet cover that represents a very efficient way of liquid cooling. Two different configurations with and without electrical insulation (TIM) were used to investigate the importance of insulating material. In the range of 10–100 mL/min coolant flow rates at an inlet temperature of 22.5 $^\circ$ C a maximum power distribution of 51 W (at 30 mL/min) next to a maximum measured mosfet temperature of 163 $^\circ$ C could be realized. Heat transfer coefficients up to 12 000 W/m $^{2}\cdot$ K were achieved using only 10.8 cm $^{3}$ of assembly space for the cooling device. With electrical insulation, the heat transfer coefficient exceeded 6000 W/m $^{2}\cdot$ K at a coolant flow rate of 30 mL/min and pumping power of 3 mW. The results illustrate the potential of direct liquid cooling using impinging microjets in combination with a compact injection chamber. The individual cooling of semiconductors offers new perspectives in the design of power electronic modules.

Latest Exposure Technology in Semiconductor Package Process

Latest Exposure Technology in Semiconductor Package Process

An analytical closed-form solution for multiple line supplier selection problem

Supplier selection is an essential issue, particularly, for semiconductor manufacturing. Nowadays, since high demands in the globally competitive semiconductor manufacturing environment, multiple-line processes are quite commonly applied. In the paper, we consider a two-stage method composing of quality verification and selection decision for multiple-line supplier selection problems. Since quality performance is an important criterion in supplier selection, we test whether the new supplier has a significantly better capability than the existing supplier based on the multiple-line yield index in the stage of quality verification. In selection decision, when the magnitude of capability outperformance is significant, switching contracts to a new entrant supplier is suggested. In addition, analytical closed-form solutions for asymptotical critical values and required sample sizes are derived and tabulated for the investigated multiple-line supplier selection problem. We demonstrate the applicability of the proposed supplier selection method by presenting a real-world example taken from a semiconductor packaging shop floor located in the Science-based Industrial Park in Hsinchu, Taiwan.

Using improved simulated anneal arithmetic to improve semiconductor packaging ball placement process capability

This study used improved simulated annealing arithmetic to improve the semiconductor packaging ball placement process capability. The simulated annealing computing process was combined with an artificial neural network, Metropolis algorithm, and sequential Gaussian simulation. Grey relation analysis was used as the target value, which is intended to obtain the optimum parameter design of process capability. The results showed that the substrate design-Pad Open is 0.30 mm ball size, 0.275 mm Pad open, Profile type B, maximum temperature 236 (°C), solder melting time 53 (s), preheating temperature 176 (°C), and a solder ball component, as SAC405 can result in a parameter design for optimal solder ball shear strength of Cpk = 2.38 and [Formula: see text]. This optimum parameter design process is better than other methods, and it reduces the cost waste of extra defectives.

Cleaner Cuts for Semiconductor Packaging

AbstractThe semiconductor packaging industry faces numerous manufacturing challenges in the production of next generation designs for advanced, miniaturized, microelectronic devices. The singulation of multiple circuits produced on a single substrate into individual devices is a standout example of this. In many instances, the cutting requirements for singulation already surpass the capabilities of mechanical cutting. Specific examples are system‐in‐package (SiP) circuitry used in wrist‐worn devices and the fingerprint sensors found in many phones, tablets or even smart watches. This leaves laser cutting as the only viable method, and both nanosecond and picosecond lasers are currently employed for these processes. This article compares these two approaches, and provides some detail on the characteristics and implementation of USP picosecond lasers for both SiP and fingerprint sensor singulation.

Physical properties of some unfilled resins employed in semiconductor packages

We have performed thermo-mechanical and electrical tests on epoxy resin samples used for semiconductor packaging applications. The reported resins are commonly used in Texas Instrument Incorporated...

Prediction of Field Failure Rate using Data Mining in the Automotive Semiconductor

Since the 20th century, automobiles, which are the most common means of transportation, have been evolving as the use of electronic control devices and automotive semiconductors increases dramatically. Automotive semiconductors are a key component in automotive electronic control devices and are used to provide stability, efficiency of fuel use, and stability of operation to consumers. Since automotive semiconductors have a high data rate basically, a microprocessor unit is being used instead of a micro control unit. For example, semiconductors based on ARM processors are being used in telematics, audio/video multi-medias and navigation. Automotive semiconductors require characteristics such as high reliability, durability and long-term supply, considering the period of use of the automobile for more than 10 years. The reliability of automotive semiconductors is directly linked to the safety of automobiles. The semiconductor industry uses JEDEC and AEC standards to evaluate the reliability of automotive semiconductors. In addition, the life expectancy of the product is estimated at the early stage of development and at the early stage of mass production by using the reliability test method and results that are presented as standard in the automobile industry. However, there are limitations in predicting the failure rate caused by various parameters such as customer’s various conditions of use and usage time. To overcome these limitations, much research has been done in academia and industry. Among them, researches using data mining techniques have been carried out in many semiconductor fields, but application and research on automotive semiconductors have not yet been studied.In this regard, this study investigates the relationship between data generated during semiconductor assembly and package test process by using data mining technique, and uses data mining technique suitable for predicting potential failure rate using customer bad data.

A Computer-aided Mold Design for Transfer Molding Process in Semiconductor Packaging Industry

This article presents a novel method for the development of a computer-aided mold design for transfer molding process in semiconductor packaging industry. The method developed will standardize mold design process and reduce lead time and costs significantly. In this method, highly robust 3D parametric templates for mold shot for different types of packages are created and stored to constitute a library for computer-aided mold design process. Mold design terms and all related design rules are standardized and streamlined for each mold shot. The mold shot is used to cut out mold parts during the next design stage. Leadframe configurations, customer input as well as technical specifications and design inputs are standardized to create the robust mold shot. Some critical features of mold parts like clamping area, location, and gate dimensions are calculated on mold shot. The mold shot is used as a positive cut-out for the top and bottom cavities as well as cull and sleeve strips. After completion of the cut-out process based on mold shot, air venting for packages and runners, clamping areas, shutoff areas, side-rail areas, relief areas, locating pins holes and their relief, misalignment pins holes and their relief are created by the rules and thumbs and mathematical formulae incorporated into the program. Finally ejection pins, support plugs, springs and other parts are created using parametric parts library and database. A prototype system “PMOLD” is developed based on is new method. This research would make a significant contribution in transfer molding and semiconductor packaging industries.

In-situ Residual Stress Analysis of Semiconductor Packaging Substrate Resins in Thermosetting Process for Investigation of their Optimum Manufacturing Process

In-situ Residual Stress Analysis of Semiconductor Packaging Substrate Resins in Thermosetting Process for Investigation of their Optimum Manufacturing Process

Contrasts in Copper Deposition on Pt(111) Modified by 1-Mercaptopropionic and 1-Mercaptoacetic Acids as Probed by Voltammetry and STM

Copper deposition on metal electrodes modified by organosulfur compounds has been extensively studied, from which some fundamental insights of this indispensable process used for semiconductor packaging have been obtained. This study employs voltammetry and scanning tunneling microscopy (STM) to examine Cu deposition on Pt(111) electrode modified with mercaptoacetic (MAA) and mercaptopropionic acids (MPA) in 0.1 M sulfuric acid containing 10−5 M CuSO4. The slight difference in the molecular structures of these organic surfactants leads to stark differences in Cu deposition. Both electrochemical and STM results show that Cu deposition proceeds much faster at the MAA- than MPA-modified Pt(111) electrode. Bulk Cu deposit grows in layers and 3D crystallites on the MAA- and MPA-modified Pt(111) electrodes, respectively. STM imaging shows that MAA and MPA modifiers segregate from the Pt(111) electrode to the Cu deposit, arranging in (√3 × √3)R30° like structures after Cu UPD, and transforming to Moire and striped patterns for bulk Cu deposition. Although MAA and MPA adsorbed on Pt(111) are both hydrogen-bonded to their neighbors, the latter has a higher degree of freedom to orient on the electrode for more intermolecular hydrogen bonds, which decreases the interaction between –COOH and Cu2+ and finally causes slower Cu deposition.

In Situ Residual Stress Analysis of Semiconductor Packages Comprising Thermosetting Encapsulation Resins and Copper Lead Frame under Thermal Process by X-ray Diffraction. Part 3

In Situ Residual Stress Analysis of Semiconductor Packages Comprising Thermosetting Encapsulation Resins and Copper Lead Frame under Thermal Process by X-ray Diffraction. Part 3