Semiconductor Packaging Research Articles

Two-Layer Rt-QFN: A New Coreless Substrate Based on Lead Frame Technology

Lead frames have been widely used in the semiconductor package assembly industry; a lot of demand is still maintained in fields requiring high reliability, such as automobiles, although many fields are being replaced by laminated substrates according to the recent electronic package product trend that requires high I/O pin count. The purpose of this paper is to introduce two-layer Rt-QFN, one of the lead frame-based coreless substrates. (Rt-QFN is a trademark of Haesung DS, which means premold type lead frame substrate.) two-layer Rt-QFN can secure more advanced design freedom compared with the lead frame and thus has I/O pin count coverage intermediate between the lead frame and laminated substrate. In addition, Rt-QFN can exhibit excellent heat dissipation performance by replacing via holes of the laminated substrate with Cu bumps formed by etching. CAE analysis showed that the thermal resistance of the two-layer Rt-QFN substrate was about 23% lower than that of the laminate substrate. The excellent heat dissipation property of two-layer Rt-QFN allows it to replace the existing expensive ceramic substrate and can achieve cost savings. In addition, the sputtering technique, including the LIS (Linear Ion Source) module, was introduced as a method to sufficiently secure the interfacial adhesion between the resin/Cu interface, which is a key factor in producing a two-layer substrate. As a method to enhance the interfacial adhesion between the resin/Cu interface, the collimated mode of LIS was used in the Ar atmosphere inside the vacuum chamber to activate the resin surface. After plasma pretreatment on the surface of the resin, a Cu seed layer was continuously formed by sputtering. As a result, it was possible to secure the high reliability of the two-layer Rt-QFN substrate, and it was confirmed through the evaluation of interfacial adhesion of more than 1.2 kgƒ/cm during the peel-off tape test at the resin/Cu interface and further moisture absorption evaluation.

Analysis on characteristic of 3.3‐kV full SiC device and railway traction converter design

With the rapid development of wide-band gap semiconductor chip and package technologies, the voltage class of commercial silicon carbide (SiC) device is gradually improved. This paper concentrates on the latest 3.3-kV full SiC-based metal oxide semiconductor field-effect transistor (MOSFET) device and its application in railway traction. First, compared with the Si-based insulated-gate bipolar transistor (IGBT), the SiC-based MOSFET shows lower switching loss but weaker short-circuit capacity. Second, in the railway traction application, the SiC-based MOSFET with high switching frequency could reduce the inverter loss, the harmonic loss and the noise of traction motor. Third, a well-designed filter is necessary between the inverter and the motor to prevent the motor from terminal overvoltage and insulation problem, which are resulted from long cable and high dv/dt. Finally, a full-SiC railway traction inverter prototype is built and tested, and shows obvious advantages on miniaturization and lightweight.

Optimization of FC-CSP and MLCC Soldering Process Using Type 7 Solder Paste

To confirm the possibility of simultaneous bonding between Si chip and multilayer ceramic capacitors (MLCCs), vacuum reflow soldering is performed between a Si chip and each of 2012, 1608, 1005, 0603, and 0402 MLCCs using Type-7 Sn-3.0Ag-0.5Cu (SAC305) and Sn-0.7Cu solder pastes. To enable an unbiased comparison with the vacuum reflow process, the Si chip and MLCCs are bonded via thermo-compression (TC) bonding and hot air reflow soldering, respectively. The maximum void content of Si chip solder joints bonded via vacuum reflow is 8%. At the MLCC solder joints, the void content yielded by vacuum reflow is lower than that yielded by hot air reflow. The bonding strength of the MLCC solder joint afforded by vacuum reflow is higher than that afforded by hot air reflow. Vacuum reflow is superior to hot air reflow in terms of the void content and bonding strength of the MLCC solder joint. After performing a thermal cycle test (TCT), a crack appeared at the Si chip solder joint bonded by TC bonding. The Cu pillar/Sn-2.5Ag bump is susceptible to cracks after the TCT owing to the insufficient bonding layer thickness yielded; however, the SAC305 sample from vacuum reflow is stable. Meanwhile, (Cu,Ni)6Sn5, Ni3P, and Ag3Sn intermetallic compounds are formed at the MLCC solder joints and then further developed after the TCT. The results of this study indicate the possibility of co-bonding Si chip with MLCCs for semiconductor packaging.

Enhancement of the Bond Strength and Reduction of Wafer Edge Voids in Hybrid Bonding.

The hybrid wafer bonding technique is drawing much interest in relation to three-dimensional integration technology, and its areas of application are expanding from image sensors to semiconductor memory packages. In hybrid bonding, the bond strength and void formation are the main issues influencing the performance, reliability, and yield of the bonding. In this study, we systematically investigate several parameters that affect both the bond strength and void formation, including the plasma gas, plasma power, and surface roughness. In particular, the effects of the wafer warpage on void formation were investigated. As O2 gas was used during plasma activation, the highest oxide growth rate and strongest bond strength were achieved. The bond strength improved when the oxide thickness was increased. An increase in the low-frequency plasma power improved the bond strength. However, when the plasma power increased further, the surface roughness increased due to the ion bombardment effect during the use of the plasma, resulting in a reduction in the bond strength. Therefore, optimization of the plasma power is required to improve the bond strength. It was found that the wafer warpage was also an important parameter which affected the formation of edge voids. The wafers with residual compressive stress exhibited fewer edge voids than those with tensile stress. Several methods to minimize edge void formation in wafers are proposed. The present study will provide practical guidelines to enhance the quality and yield of the bonding process and devices.

Motion performance measurement and optimization of motorized stages using tightly focused laser marking

Motorized stages are widely used in the fields of processing and measurement, such as lithography, semiconductor packaging, biochips, and micro/nanostructure characterization. We propose a tightly focused laser marking method for measuring the motion performance of motorized stages. In this method, a test sample is coated with heat-mode resist thin films and is fixed onto motorized stages. A tightly focused laser spot with a size of ∼520 nm irradiates the heat-mode resist thin films, which then absorb the laser energy and are heated. A laser-induced marking of the films’ structural change from an amorphous state to a crystalline state occurs when the temperature exceeds the crystallization threshold temperature. The motion locus and performance of motorized stages can be clearly observed via the marking of the structural change of heat-mode resist thin films, which can be further clarified through the lithography developing process in alkaline or acidic solutions. The measurement results showed that the minimum nonuniformity coefficient of the motorized stages was 0.016, the minimum parallelism error was 80 nm, the minimum positional accuracy was 0.76 μm, and the accuracy of the measurement system was within 80 nm. The test results demonstrate that the motorized stage can achieve high-precision uniaxial motion with a period of 300 nm and biaxial coordinated motion with a period of <3 μm through parameter optimization, thereby reaching its ultimate performance. Compared to the non-interferometric methods, this tightly focused laser marking method has the advantages of strong environmental adaptability and high accuracy. This study provides an effective and convenient approach for the measurement and optimization of the motion performance of motorized stages.

Copper to resin adhesion characterization for power electronics application: Fracture toughness and cohesive zone analysis

The use of molding compound as encapsulant is nowadays increasing in semiconductor power module applications. The adhesion of package interfaces between copper components and molding compound is one of the key aspect for an improved durability. The presented activity proposes the fracture toughness characterization of copper–resin interface in a power semiconductor package due to different experimental tests and the cohesive zone method to describe interfacial fracture. Double Cantilever Beam (DCB) and Four Point Bending (FPB) tests have been executed on dedicated bi-material coupons. The scope of these trials has been to enhance two different propagation modes based on different ratio between mode-I (opening) and mode-II (sliding) according to a mixed-mode approach. Strain energy release rate (SERR) and mode-mixity have been estimated by a finite element analysis based on the virtual crack closure technique (VCCT) and the crack surface displacement method (CSD). The information about fracture toughness at two different mode mixity have been considered to predict the SERR for every arbitrary mode mixity. Finally, dedicated finite element models based on cohesive elements have been developed and calibrated considering the fracture toughness experimental values and the measured force–displacements behavior during the two considered tests. Dedicated physical analyses have been carried out to validate the proposed method.

Simulation methodology development of warpage estimation for epoxy molding compound under considerations of stress relaxation characteristics and curing conditions applied in semiconductor packaging

The thermal mismatch between different components has been a serious issue in the reliability of electronic products. The effect of epoxy molding compound (EMC) on the warpage of electronic package should be considered. The finite element method (FEM) is widely adopted to predict the warpage induced by the molding process. However, no previous studies focused on the warpage during the molding process and post process. In this study, several material characteristics of the EMC, such as cure reaction, cure shrinkage, and viscoelasticity, are measured. This study analyzes the corresponding mathematical model completely and substitutes the above properties into the FEM while the process conditions are considered through measurement. A process-oriented simulation methodology is proposed, and the estimated warpage results show that the simulation methodology with stress relaxation of EMC is in good agreement with the experimental value. The characteristics of stress relaxation behavior undergoing the molding process are discussed through the evolution of warpage. The warpage is different from the two process steps at room temperature due to the stress relaxation. This study demonstrates how the conditions of the post molding cure (PMC) process affect the warpage. The warpage can decrease with the extension of PMC time but the degree of reduction has a limit.

Sulfur Ingression on Encapsulated Leadframe of Discrete Semiconductor Package

Methanesulfonic acid (MSA) has been widely used in the electroplating step at a backend semiconductor assembly process. This process comes after component encapsulation, which serves primarily to protect internal components of a device as well as to prevent ingression of chemical byproducts. The objective of this article is to study sulfur (S) ingression activities with respect to both electroplating and encapsulation processes and their effect on leadframe surface conditions. This can be achieved through observation of leadframe surface condition on samples prepared through laser ablation or mechanical decapsulation. Results from 17 engineering lots show that 25% of samples analyzed were observed with leadframe surface irregularities. The energy-dispersive X-ray spectroscopy (EDX) analysis confirmed the trace of S element on the area with surface irregularities, which can be linked to S ingression based on the trace of its path from outside, probably due to the existence of a microgap on the package. These findings provide a clearer understanding of the ingression path of S for encapsulated copper (Cu) leadframe. Even though ingression of S does not directly cause a failure, it is thought that this could act as a precursor to further failure mechanisms such as corrosion-like phenomena.

Hardware Engineer’s Guide to a Brushless-DC Motor Controller: Design and challenges

Brushless-dc (BLDC) motors have best-in-class torque to weight ratio, high efficiency, and effective control algorithms, which make them effective solutions in applications requiring high power density, such as cordless power and garden tools, unmanned aerial vehicles (UAV), robotics, and others. Improvements in semiconductor packaging technology, motor control algorithms, and power management integrated circuits (ICs) have increased the industrial uptake of BLDC motors. High-power battery-powered motor-drive solutions require power levels ranging from a few watts to hundreds or even thousands of watts. High wattage systems require high motor currents, resulting in design challenges of system losses and thermal management. A system designer&#x2019;s challenge is to accommodate all the functionalities of a motor controller in a compact form for the whole range operation. Typically, a motor controller uses an analog signal chain, analog power management, and digital components with both signal and power traces on the same board. A well-designed printed circuit board (PCB) is required for the system to operate efficiently. This article lays the guidelines for designing a BLDC motor drive PCB.

Drive to Squeeze More Power From Tiny Packages, On-Chip Substrates Continues Unabated [From the Editor

The fervor for miniaturization continues in the power supply world. Power supply designers have kept pace with the demands of the market for more power from smaller packages with better efficiency, reliability, and speed. While keeping the cost low. Consequently, power integration, both in package and on-chip, has continued to evolve for more than a decade. The result is that power supply in package (PSiP) and power supply on-chip (PwrSoC) have become mainstream products, driven by traditional and emerging applications. Today, we are talking about hundreds of watts from a compact semiconductor package, as well monolithic semiconductor substrates.

Driven by Density, Efficiency at Low Cost, Power Integration Reaches New Heights: PSiPs and PwrSoCs are growing faster than the traditional power supplies

For decades, miniaturization has been the trend in the power supply world. Consumers have been demanding more functions from smaller systems with better performance and reliability at lower cost. Such advances are evident in today’s laptops, tablets, smartphones, industrial drives and a host of other consumer and industrial applications. To meet these demands, the power supply industry has also kept pace with the needs of the markets. As a result, power integration, both in package and on-chip, has continued to evolve for more than a decade. Consequently, with this evolution, power density has risen from tens of watts to hundreds of watts from compact semiconductor packages with high performance in efficiency, density, reliability and other such metrics. On-chip, we are talking about tens of watts delivered from monolithic semiconductor substrates.

Effect of critical properties of epoxy molding compound on warpage prediction: A critical review

For the past couple of decades, a considerable amount of time and effort has been spent to enhance the predictability of warpage of semiconductor packages encapsulated by epoxy molding compound (EMC). With advanced computational mechanics techniques and computing hardware, one can simulate almost any kind of packages. Thermo-mechanical properties required for numerical predictions, including the coefficient of thermal expansion (CTE), the glass transition temperature (Tg), and the temperature and time-dependent viscoelastic properties, are routinely measured by commercial tools such as thermo-mechanical analyzer (TMA) and dynamic mechanical analyzer (DMA). In addition, temperature-dependent warpage can be measured readily using commercial tools based on shadow moiré and digital image correlation (DIC). In spite of this considerable effort, accurate prediction remains a challenging task. EMC typically occupies a large portion of package volume, and thus plays a major role in package warpage behavior. This review paper examines the effect of critical EMC properties on warpage behavior. Based on the data and the analyses reported in the literature, the paper addresses three potential causes that make the prediction still difficult, and discusses what should be done to bring the prediction capability to a desired level.

Solder void size reduction in semiconductor package by vacuum reflow and pressure cure processes

PurposeSemiconductor packaging industry has in recent years tightened the tolerance criteria for acceptable solder void size in the semiconductor packages due to the high usage in automotive applications. Semiconductor packaging component makers have strengthened the quality of the solder joint and its electrical conductivity by controlling the maximum solder void size reduction from 10-15% to 5% or below over die size. This paper aims to reduce the solder void size to minimum level that current industry could not achieve and introduce a new soldering processes by combining vacuum reflow and pressure cure to effectively reduce solder void.Design/methodology/approachThis study is using the empirical data collection to prove the feasible in achieve the goal. It is an engineering approach. This research study is even considering sufficient data (>22 units) in each evaluation to represent the actual performance.FindingsSuccessfully eliminate all the hollow solder void that current industry claimed as solder void. EDX analysis showed that the compressed solder voids remained in the solder are filled with solid carbon-based substances which could be originated from the trapped flux residues. It is empirical data proven in feasibility stage.Research limitations/implicationsThe study is able to produce solder void-less. This method is suitable for high volume manufacturing process also. This may lead a new pave way for industry to resolve solder void problem. The current pressure cure machine could not apply more than 200°C temperature which limits medium and high temperature solder paste or alloy testing. Therefore, only low temperature solder alloy Pb37Sn63 was able to be evaluated.Originality/valueThis study is original and has not been published elsewhere to produce high efficiency product in semiconductor packaging performance in electrical path and heat dissipation. It also improves package reliability due to solder joint used as interconnect in semiconductor packaging.

REMOVED: Catalysis of reduced tin oxide in various epoxy resins

Epoxy resins are the most widely used thermoset materials for various applications, including electronic devices such as semiconductor packaging. In this study, tin (Sn) catalysis in diverse epoxy binary systems containing amine, acid or anhydride was explored by using various differential scanning calorimetry (DSC) techniques and rheological properties. Catalytic effects of Sn were observed in epoxy–anhydride and epoxy–diacid systems but not in epoxy–amine systems. For instance, the incorporation of 1 vol% Sn into the epoxy–succinic anhydride and epoxy–pimelic acid systems reduced the DSC exothermic peak temperature from 295 °C to 202 °C and 243–196 °C, respectively. By contrast, Sn presented no catalytic effect in epoxy–amine systems. Sn catalysis was investigated using isothermal curing temperatures and time. The onset temperature during viscosity measurements for the epoxy–anhydride and epoxy–diacid systems substantially decreased as a function of Sn concentration. These catalytic effects of Sn metal particles (oxidized in air) in the epoxy–anhydride and epoxy–diacid systems can be utilized to accelerate the reactions of epoxy resins and to anticipate the reaction conditions in various applications such as electronic devices involving Sn and epoxy resins. • Sn catalysis was observed in epoxy-anhydride and epoxy-diacid curing systems. • Epoxy-amine curing system did not show the Sn catalytic effect. • Various DSC and rheometry measurement techniques were used. • Latent catalytic effects were also examined.

Coalescence kinetics and microstructure evolution of Cu nanoparticles sintering on substrates: a molecular dynamics study

Nano copper sintering technology has great potential to be widely applied in the wide-bandgap semiconductor packaging. In order to investigate the coalescence kinetics of copper nano particles for this application, a molecular dynamic (MD) simulation was carried out at low temperature on a special model containing two substrate and multiple particles in between. Accordingly, thorough microstructure and dislocation investigation was conducted to identify the atomic-scale evolution in the system. The corresponding findings could provide evidence on the new particle-substrate sintering mechanism. Furthermore, atomic trajectories tracking method was applied to study the rotation behavior of different sized nano particles. New rotation behavior and mechanism were described. Additionally, the study on the size effect of copper particles on the sintering process and coalescence mechanism was conducted via comparing the microstructural and dislocation distribution of 3 nm, 4 nm and 5 nm models. Finally, by comparing the MSD results at low and high temperature for each model, the dominant coalescence dynamics changes were obtained.

Enhanced Thermal Conducting Behavior of Pressurized Graphene-Silver Flake Composites.

Modern electronics continue to shrink down the sizes while becoming more and more powerful. To improve heat dissipation of electronics, fillers used in the semiconductor packaging process need to possess both high electrical and thermal conductivity. Graphene is known to improve thermal conductivity but suffers from van der Waals interactions and thus poor processibility. In this study, we wrapped silver microflakes with graphene sheets, which can enable intercoupling of phonon- and electron-based thermal transport, to improve the thermal conductivity. Using just 1.55 wt % graphene for wrapping can achieve a 2.64-times greater thermal diffusivity (equivalent to 254.196 ± 10.123 W/m·K) over pristine silver flakes. Graphene-wrapped silver flakes minimize the increase of electrical resistivity, which is one-order higher (1.4 × 10-3 Ω·cm) than the pristine flakes (5.7 × 10-4 Ω·cm). Trace contents of wrapped graphene (<1.55 wt %) were found to be enough to bridge the void between Ag flakes, and this enhances the thermal conductivity. Graphene loading at 3.76 wt % (beyond the threshold of 1.55 wt %) results in the significant graphene aggregation that decreases thermal diffusivity to as low as 16% of the pristine Ag filler. This work recognizes that suitable amounts of graphene wrapping can enhance heat dissipation, but too much graphene results in unwanted aggregation that hinders thermal conducting performance.

Investigation of integrated factors in the occurrence of copper wire bonding corrosion of semiconductor packages

Copper wire bonding has got attracted attention over gold wire bonding due to its lower cost. However, despite many unique aspects and properties of copper wire bonding, corrosion of copper wire bonding has become a point of interest as it leads to the failure of semiconductor packages. Current and future trends and development in miniaturization and multifunction of the semiconductor packages show semiconductor manufacturers to establish good wire bonding with high reliability. However, this trend becomes a significant challenge in respect of corrosion occurrence. Several studies on the corrosion of copper wire bonding; however, there is no considerable study in the integrated factors leading to corrosion. Therefore, this paper focuses on investigating the corrosion phenomena of wire copper wire bonding, especially wedge bonds. This paper use a combination of the problem-solving approach for a complex problem. The analysis suggested that the weightage of factors, depending on process parameters and process steps, play a particular role in facilitating or preventing corrosion on the copper wire bonding. Therefore, it is essential to consider these factors when designing assembly process steps and parameters to control corrosion in semiconductor packages.

Application of Convolutional Neural Network to Predict Anisotropic Effective Thermal Conductivity of Semiconductor Package

Application of Convolutional Neural Network to Predict Anisotropic Effective Thermal Conductivity of Semiconductor Package

Evaluation of Fatigue Crack Propagation Rate at the Interface between Si Die and Underfill in Real Semiconductor Package Structures

In this study, fatigue crack growth rate at Si/UF interface was evaluated by four-point bending fatigue crack growth tests. At the bottom of the Si die, the fatigue crack growth behavior was similar to that of the UF bulk, in which the transition from the threshold to steady-state crack growth was observed. The power exponent of the Paris law in the steady-state region was similar to that of the UF bulk, and the fatigue crack growth rate was different between the side and bottom of the Si die. These results suggest that the fatigue crack growth behavior at the interface strongly depends on the surface roughness of the Si die and the manufacturing process of underfilling.

Melamine-graphene epoxy nanocomposite based die attach films for advanced 3D semiconductor packaging applications.

With the ultra-fast development of personal portable electronic devices, it is important to explore new die attach film (DAF) materials in the limited mounting area and height in order to meet the requirements of a high packaging density and a high operating speed. Graphene-based epoxy nanocomposites are becoming one of the most promising candidates for the next generation of DAFs combining the ultra-high thermal conductivity of graphene, and ultra-strong adhesion of epoxy polymers. However, poor dispersion and weak interfacial connections, due to the overly smooth surface of graphene nanosheets, are still pressing issues that limit their industrial applications. Additionally, pristine graphene nanosheets have only a small effect on improving the glass transition temperature (Tg) of epoxy composites to meet the requirements of DAFs. In this work, melamine-functionalized graphene is synthesized by using a nondestructive ball milling process, which results in greater dispersion and enhancement of the interfacial connections between graphene and epoxy resins demonstrated by both experimental and simulation results. In particular, the aromatic triazine rings of melamine increase Tg in the cured resin, thus improving the thermal stability of DAFs. The melamine-graphene (M-G) epoxy nanocomposites synthesized have a high Tg of 172 °C and an out-of-plane thermal conductivity of 1.08 W m-1 K-1 at 10 wt% loading. This is 6.4 multiples higher than that of neat epoxy. Moreover, M-G epoxy nanocomposites exhibit superb thermal stability, an effective low coefficient of thermal expansion (CTE), low moisture adsorption, and a useful high electrical resistivity. In the DAF performance test, involving experimentation and modeling, the samples present a better cooling capability and heat dissipation. This supports the idea that our findings have potential to be applied in the next generation of DAFs for high-power and high-density 3D packaging.