Packaging Renaissance with Chiplets

Abstract

Abstract With ever shrinking advanced CMOS nodes and evolution of systems with increasing complexity, the traditional SoC paradigm is facing extensive challenges in terms of yields and heterogeneity. The emerging industry solution to this has been to partition the SoCs into smaller units, with each unit performing a certain (though exclusive) function. This drove the birth of “chiplets”. With advent of chiplets, the traditional function of packaging as an after-thought to chip development has got a revolutionary face-lift. Packaging is now enabling interconnects to replace on-chip global interconnects. The onus now is on packaging to get the chiplets to integrate and communicate with each other such that the net performance is equivalent to or better than SoC. This has spawned a renaissance in field of semiconductor packaging, with newer multi-die packaging technologies being productized to realize newer and better interconnects. Some examples of these emerging technologies include advanced flip-chip, 2.5D, 2.1D, 3D, Wafer Level Fan-Out, and Bridge Technologies. AMD is at forefront of chiplet technologies, with extensive 7nm chiplet based product portfolio catering to the HPC market. This talk will discuss the current state of chiplet packaging technologies.