Silicon Wafer Integrated Fan-out Technology

Abstract

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need. These include Through Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP) approaches. In particular, emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Traditional WLFO technologies are limited in design rules and 3D integration capabilities due to the processes and equipment used for circuit patterning. For more aggressive designs, TSV processes must be incorporated, which often times exceed the cost budget and design requirements needed for the device. Consequently, a gap exists between the design capabilities of WLFO and TSV that needs to be addressed. A new, innovative fan-out structure called Silicon Wafer Integrated Fan-out Technology (SWIFT™) packaging incorporates conventional WLFO processes with leading-edge thin film patterning techniques to bridge the gap between TSV and traditional WLFO packages. The SWIFT methodology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single and multi-die applications. The improved design capability of the technology is due, in part, to the fine feature capabilities associated with this new, innovative wafer-level packaging technique. The fine feature capabilities can allow much more aggressive design rules to be applied compared to competing WLFO and laminate-based technologies. In addition, the unique characteristics of the SWIFT process enable the creation of innovative 3D structures that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of the SWIFT technology and its extension into unique 3D structures. In addition, the advantages of SWIFT designs will be reviewed in comparison to current competing packaging technologies. Process information, material characterization, and design simulation data will be presented to show how the SWIFT process is poised to provide robust, reliable, and low-cost 3D packaging solutions for advanced mobile and networking products. SWIFT is a trademark of Amkor Technology, Inc.