Heterogeneous Integration Challenges Within Wafer Level Fan-Out SiP for Wearables and IoT

Abstract

Expanding WLFO (Wafer Level Fan-Out) packaging with all its advantages, from mainly 2D single-die and side-by-side multi-die solutions to 3D stacked, multi-die solutions, is extremely important to accommodate the requirements of new markets and applications such as wearables and the Internet of Things (IoT). This need drives the development of a new set of capabilities in the current standard WLFO process flow to break through the current technology boundaries. One of the most discussed advantages of WLFO is the high-density heterogeneous system integration in a package. Wafer Level Fan Out System-in-Package (WLFO SiP) integrates active dies, passive components and even already-packaged components using other packaging technologies. This diverse integration is based on a wide range of different geometries and materials, and placed inside the WLFO SiP with high accuracy. The WLFO SiP process for high volume was demonstrated with test vehicles of multi-chip package of 7.5 x 12.6 mm2 with two fine-pitch redistribution layers (RDLs) connecting 26 components. Through package vias (TPV) and back-side RDL were used on this SiP for Package-on-Package (PoP) applications. The WLFO test units were submitted to 1st level reliability tests based on functional test. The work done for this paper is part of the collaborative COMPETE2020-PT2020 funding program under IoTiPInternet of Thing in Package project no 017763, Projetos de I&DT Empresas em CoPromocao.