Nanosheet Field-effect Transistors Research Articles

In-line Raman spectroscopy for gate-all-around nanosheet device manufacturing

In-line Raman spectroscopy for compositional and strain metrology throughout front-end-of-line (FEOL) manufacturing of next-generation gate-all-around nanosheet field-effect transistors is presented. Thin and alternating layers of fully strained pseudomorphic Si(1 − x)Gex and Si were grown epitaxially on a Si substrate and subsequently patterned. Intentional strain variations were introduced by changing the Ge content (x = 0.25, 0.35, 0.50). Polarization-dependent in-line Raman spectroscopy was employed to characterize and quantify the strain evolution of Si and Si(1 − x)Gex nanosheets throughout FEOL processing by focusing on the analysis of Si-Si and Si-Ge optical phonon modes. To evaluate the accuracy of the Raman metrology results, strain reference data were acquired by non-destructive high-resolution x-ray diffraction and from destructive lattice deformation maps using precession electron diffraction. It was found that the germanium-alloy composition as well as Si and Si(1 − x)Gex strain obtained by Raman spectroscopy are in very good agreement with reference metrology and follow trends of previously published simulations.

The influences of radiation effects on DC/RF performances of L g = 22 nm gate-all-around nanosheet field-effect transistor

In this paper, we carried out detailed technology computer aided design simulations to investigate the radiation effects, e.g. total ionizing dose (TID) and single-event effects (SEEs), on direct current (DC) and radio frequency (RF) characteristics of the gate-all-around (GAA) nanosheet field-effect transistor (FET). The simulation model used is composed of seven-layer stacked GAA nanosheet FET with L g = 22 nm, which was implemented in this study. The open current and the drain-induced barrier lowering of the device are ∼3 mA μm−1 and 47 mV V−1, respectively. The results indicate that the TID have little influence on the DC and RF characteristics when the transistor is working in an open state. During the SEEs simulation, we considered three incident directions for the high energy particle, including the lateral direction of the channels, the vertical direction of the channels and the top of the channels. The influence of the particle injecting along the lateral and vertical directions of the channels shows stronger relation with the distance from the incident point compared to the influence of the particle from the top. Besides, the general influence of the particle injecting along the lateral directions of the channels is higher than the other two directions. The total injected charge of the particle injecting along the lateral direction, along the vertical direction and from the top are 3 fC, 1.4 fC and 2.1 fC, respectively. As compared to the fin FET, the GAA nanosheet has superior RF performances and less sensitivity to TID effect. This work can provide a guideline for the GAA nanosheet devices in aerospace and avionic RF applications.

Comprehensive performance enhancement of a negative-capacitance nanosheet field-effect transistor with a steep sub-threshold swing at the sub-5-nm node

A nanosheet field-effect transistor (NSFET), which has excellent gate control ability, has been considered as the most attractive key architecture that may replace the FinFET below a 5-nm technology node. In this study, a three-dimensional (3D) technology computer-aided design (TCAD) simulation is carried out to evaluate and compare the performance of a negative-capacitance NSFET (NC-NSFET) with an NC fin field-effect transistor (NC-FinFET). The result shows that under the same structural parameters, the NC-NSFET has a higher on-current- to-off-current ratio (Ion/Ioff), and lower sub-threshold swing (SS) and drain-induced barrier lowering (DIBL) than the NC-FinFET. The analog/radio frequency (RF) performance enhancement of the NC-NSFET shows that the NC-NSFET has higher transconductance (gm) and cutoff frequency (fT) at a lower drain voltage (Vds) than the conventional NSFET has. In addition, a negative correlation between fT and SS, which is determined and verified for the first time, reveals that the NC-NSFET enabling analog/RF performance improvement is attributed to the higher ratio of the drain current to the SS.

DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors

Grain boundary (GB) at the source/drain (S/D) epitaxy was investigated using fully-calibrated TCAD. Because the S/D epi is grown separately at the bottom and the NS channels, nanosheet field-effect transistors (NSFETs) have unwanted GB within the S/D epi which fully relaxes the channel stresses. This GB changes the doping profiles and the stress values, which thus degrade the DC performances. We focused on single GB with different inclined angles and positions. N-type NSFETs have similar DC performances regardless of the GB since the changes of doping and stress were small. P-type NSFETs suffer from DC performance degradations but different depending on the GB positions. As the GB splits the p-type S/D epi into two, lower S/D below the GB has tensile stress and upper S/D above the GB has compressive stress. Since tensile stress increases boron diffusivity, more boron dopants diffuse into the NS channels as the device has lower S/D region, thus suffering the short channel effects greatly. The device having upper S/D region loses the channel stress much, so it degrades the on-state performance. This study provides clear understanding of the GB effects of NSFETs.

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ </tex-math></inline-formula> ) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.

Performance analysis of nanowire and nanosheet NCFETs for future technology nodes

Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In addition to single channel NC-NSFETs and NC-NWFETs, those, with vertically stacked NSs and NWs, have been examined for the same layout footprint (LF). Results show that NC-NSFETs can achieve lower subthreshold swing (SS) and higher ON-current (I ON ) than NC-NWFET of comparable device dimensions. However, NC-NWFETs show slightly higher I ON /I OFF ratio. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths as small as 10 nm. The results presented here can, therefore, provide useful insights for performance optimization of NC-NWFETs and NC-NSFETs, in ultra-scaled and high-density logic applications, for 7 nm and beyond technology nodes.

Simulation-Based Study of High-Permittivity Inserted-Oxide FinFET With Low-Permittivity Inner Spacers

A high-permittivity (high- ${k}$ ) inserted-oxide FinFET (iFinFET) structure with low-permittivity inner spacers is proposed for CMOS transistor scaling to the 3-nm technology node and beyond. The process to fabricate an iFinFET is similar to the process to fabricate a nanosheet field-effect transistor (NSFET); no additional lithography masks are needed. Unlike the NSFET and the nanowire field-effect transistor (NWFET), which each require significant spacing between the nanosheets or nanowires (NWs) to accommodate metallic gate and dielectric insulator multilayer stacks, the iFinFET requires only a single ultrathin high- ${k}$ inserted-oxide (i-oxide) layer between the NWs, allowing more NWs to be vertically stacked within the constraint of a maximum total channel height. The i-oxide layers serve to allow fringing electric fields from the gate to penetrate into the NWs to achieve improved electrostatic integrity. Simulated performance characteristics of the proposed iFinFET structure are compared against those for the FinFET, NWFET, and NSFET. The iFinFET is projected to achieve the best electrical performance when the footprint (device layout width) is less than 80 nm.

A Comprehensive Investigation of Vertically Stacked Silicon Nanosheet Field Effect Transistors: an Analog/RF Perspective

In this article, the analog/RF performance of n-channel vertically stacked gate all around (GAA) silicon nanosheet field effect transistors (Si-NSFETs) are investigated using 3-D TCAD simulations. The influence of gate length (LG) scaling, nanosheet width (WNS) and spacing between the nanosheets on the analog/RF performance of vertically stacked GAA Si-NSFET with two nanosheets are explored. The 3-D TCAD simulations indicates that reducing LG from 20 nm to 12 nm results in the improvement of RF performance in terms of increased gm (transconductance), drive current, fT (cut off frequency), fmax (maximum oscillation frequency) and degradation of analog performance in terms of reduced intrinsic gain. 3-D TCAD simulations also shows that increasing the WNS from 10 nm to 18 nm leads to the enhancement of gm and drive current, does not affect the fT and degrades the intrinsic gain due to the increase of drain conductance and gate capacitance. It is also observed that the spacing between the nanosheets does not have any significant impact on analog/RF performance of vertically stacked GAA Si-NSFETs. Consequently, the vertically stacked GAA Si-NSFETs with lower LG and higher WNS will be more suitable to realize both flash memory and dynamic random access memory (DRAM) for improved performance owing to their better RF performance.

Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process

We presented and demonstrated a new type of vertical nanowire (NW) and nanosheet (NS) field-effect transistors (FETs), named vertical sandwich gate-all-around FETs or VSAFETs, which were formed with the process compatible in the main stream industry. The VSAFETs with self-aligned high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> metal gates (HKMGs) were fabricated with epitaxy of Si/SiGe/Si sandwich structure, an isotropic quasi-atomic-layer-etch (qALE) process, and gate replacement process. The gate-length of VSAFETs is mainly determined by the thickness of SiGe film grown by epitaxy. The NW diameter and NS thickness could be obtained by the isotropic qALE method, which can be used to the Si-selective etching of SiGe. As a result, p-type NS and NW VSAFETs with good device characteristics were fabricated. Device performance and the influence of silicide, Ge fraction, Si cap, and high thermal process were investigated; threshold voltage tuning and reliability were also discussed.

TID Circuit Simulation in Nanowire FETs and Nanosheet FETs

In this study, the effects of the total ionizing dose (TID) on a nanowire (NW) field-effect transistor (FET) and a nanosheet (NS) FET were analyzed. The devices have Gate-all-around (GAA) structure that are less affected by TID effects because GAA structures have better gate controllability than previously proposed structures, such as planar MOSFETs and FinFETs. However, even for GAA devices with the same channel cross-sectional area and equivalent oxide thickness, structural differences can exist, which can result in different tolerances of TID effects. To observe the device and circuit operation characteristics of these GAA devices with structural differences, n-type and p-type devices were designed and simulated. The circuit simulation according to TID effects was conducted using Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. The NS-FET generated more VT shift than the NW-FET because the NS-FET had a wider gate oxide area and channel circumference, resulting in more interface hole traps. The abnormal VT shift leads to causing unstable circuit operation and delays. Therefore, it was confirmed that the ability of the NW-FET to tolerate TID effects was better than that of the NS-FET.

Defect spectroscopy of sidewall interfaces in gate-all-around silicon nanosheet FET

Through time-dependent defect spectroscopy and low-frequency noise measurements, we investigate and characterize the differences of carrier trapping processes occurred by different interfaces (top/sidewall) of the gate-all-around silicon nanosheet field-effect transistor (GAA SiNS FET). In a GAA SiNS FET fabricated by the top-down process, the traps at the sidewall interface significantly affect the device performance as the width decreases. Compare to expectations, as the width of the device decreases, the subthreshold swing (SS) increases from 120 to 230 mV/dec, resulting in less gate controllability. In narrow-width devices, the effect of traps located at the sidewall interface is significantly dominant, and the 1/f 2 noise, also known as generation–recombination (G–R) noise, is clearly appeared with an increased time constant (τ i ). In addition, the probability density distributions for the normalized current fluctuations (ΔI D) show only one Gaussian in wide-width devices, whereas they are separated into four Gaussians with increased in narrow-width devices. Therefore, fitting is performed through the carrier number fluctuation-correlated with mobility fluctuations model that separately considered the effects of sidewall. In narrow-width GAA SiNS FETs, consequently, the extracted interface trap densities (N T ) distribution becomes more dominant, and the scattering parameter () distribution increases by more than double.

A Physical Model for Bulk Gate Insulator Trap Generation During Bias-Temperature Stress in Differently Processed p-Channel FETs

A deterministic reaction-diffusion–drift model is used for the time kinetics of bulk gate insulator trap generation in p-channel Field Effect Transistors (FETs) under inversion stress. The consistency of the deterministic and stochastic versions of the model is shown. The model is independently validated using stress-induced leakage current data from various reports. The model is incorporated into the already existing bias temperature instability (BTI) analysis tool framework and validated using negative BTI data. The measured data from FinFETs having different channel material, substrate type, gate insulator process, and fin length, as well as gate-all-around stacked nano sheet (GAA-SNS) FETs are modeled.

Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs

Through-silicon via (TSV)-induced mechanical stress and electrical noise coupling effects on sub 5-nm node nanosheet field-effect transistors (NSFETs) were investigated comprehensively compared to fin-shaped FETs (FinFETs) using TCAD for heterogeneous 3D-ICs. TSV-induced channel length directional stress ( $S_{ZZ}$ ) predominantly causes variations of on-state current ( $\Delta I_{on}$ ). NSFETs exhibit the greater $\Delta I_{on}$ than FinFETs because electron velocities and densities in channels vary with respect to $S_{ZZ}$ in the same directions for NSFETs but do the opposite for FinFETs. Nevertheless, TSV-induced mechanical stress is negligible when TSV is farther than keep-out zone. Meanwhile, TSV signals can be coupled to operating devices through substrate and induce capacitive and back-bias noise coupling currents ( $I_{cap}$ , $I_{b-b}$ ). NSFETs exhibit the greater $\vert I_{cap}\vert /I_{on}$ than FinFETs because its wider source/drain (S/D) epitaxies form larger depletion capacitances between drain and punch-through stopper (PTS). On the other hand, the $\vert I_{b-b}\vert /I_{on}$ is smaller for NSFETs because its parasitic bottom transistor alleviates back-bias-induced potential barrier lowering. Furthermore, wide diameter of Cu of TSV increases $\vert I_{b-b}\vert /I_{on}$ only, but short rise time of TSV signals increases both $\vert I_{cap}\vert /I_{on}$ and $\vert I_{b-b}\vert /I_{on}$ . Unfortunately, conventional devices cannot satisfy criterion for analog applications ( $\vert I_{cap}$ , $I_{b-b}\vert /I_{on} %); therefore, a new strategy inserting bottom oxide (BOX) beneath the S/D with undoped PTS is suggested. The $\vert I_{cap}\vert /I_{on}$ for NSFETs decreases by undoped PTS, but not for FinFETs due to a remnant depletion capacitance between fin and PTS. The $\vert I_{b-b}\vert /I_{on}$ for NSFETs decreases remarkably due to completely blocked $I_{b-b}$ path, but FinFETs still have $I_{b-b}$ path under the fin. Therefore, NSFETs with BOX and undoped PTS are the most suitable for sub 5-nm node heterogeneous 3D-IC, especially in analog applications.

Design optimization of sub-5 nm node nanosheet field effect transistors to minimize self-heating effects

In this work, self-heating effects (SHE) in nanometer-scale metal-oxide-semiconductor field-effect transistor structures—namely, FinFETs (FFs), nanosheet gate-all-around FETs (NSFs), and nanowire gate-all-around FETs (GAAFs)—are investigated via three-dimensional device electrothermal simulations using technology computer-aided design software tools. Initially, transistor design parameter values are set so that their on-state currents are similar for the same operating voltage (VDD). It is found that NSFs and GAAFs are more susceptible to SHE and that p-channel transistors have higher peak internal temperatures than do their n-channel counterparts due to the poor thermal conductivity of the silicon-germanium used as the p-type source/drain material. Subsequently, the on-state currents of FFs, NSFs, and GAAFs are compared under the constraint of identical peak internal temperature, which is required to ensure long-term reliability, revealing that NSFs and GAAFs offer no performance advantage over FFs under this constraint. Design optimization of p-channel NSFs for minimal SHE is subsequently investigated. It is found that with such optimization, NSFs operating at lower VDD (for similar SHE) can achieve similar on-state current as FFs.

Comparing bulk-Si FinFET and gate-all-around FETs for the 5 ​nm technology node

In this paper, bulk CMOS finFET, horizontal gate-all-around (GAA) nanowire and nanosheet field-effect transistors are compared for the 5 ​nm technology node. The performance of these transistors and the circuits comprising them is assessed through 3-D technology computer-aided design (TCAD) simulations and circuit level SPICE simulations of BSIM compact models calibrated to the TCAD results, respectively. Full parasitic extraction is used on standard cell and static random access (SRAM) memory cell layouts to ensure accurate delays. The target of this work is a 5 ​nm technology node follow-on to an existing 7 ​nm predictive process design kit (PDK) in common academic use. Subthreshold slope, drain induced barrier lowering, gate-induced drain leakage and subthreshold current are compared for different gate lengths. Transistor performance is also compared for various raised source/drain lengths and low-k gate spacer widths. The gate-all-around field-effect transistors show better electrostatic performance as expected. However, the simulation results show that finFET devices will be adequate at the 5 ​nm node, should the GAA devices prove to be difficult to produce in high volume manufacturing.

The Impact of Displacement Defect in Nanosheet Field Effect Transistor

Anomalies due to random displacement defect is investigated in a 5 nm nanosheet gate-all-around field effect transistor (NS-FET). Terrestrial cosmic radiation is known to cause silicon displacement in random location. In this work, the random displacement anomaly (RDA) is investigated in NS-FET with the aid of technology computer aided design (TCAD). The fluctuation due to RDA is considered as a variable and its impact on the electrical characteristics is investigated for various width and thickness values of the NS-FET. The contribution to the RDA in individual NS layers is studied. The worst degradation rate of drain current is almost 20% while RDA is located at center of top layer in NS-FET.

Exploration of Negative Capacitance in Gate-All-Around Si Nanosheet Transistors

Gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) are the most promising candidates to replace FinFETs and nanowire (NW) FETs in future technology nodes owing to their improved short-channeleffects, high current drivability per layout footprint (LF), and extreme scalability. The much-needed voltage scaling in these aggressively scaled devices can be provided by introducing negative capacitance (NC) effect, which results in sub-60 mV/decade switching behavior. In this article, we explore how NC effect manifests into silicon NS transistors by using technology computer aided designs (TCAD). The NC effect originates from a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) configuration in the gate-stack. The performance of single channel NC-NSFET is benchmarked against NC-NWFET and NC-FinFET of comparable device dimensions. NC-NSFET shows 9% and 38% lower subthreshold swing when compared to NC-NWFET and NC-FinFET, respectively. For NC-NSFETs, capacitance matching, between the ferroelectric (FE) and the underlying MOS capacitance, is achieved with a thinner FE layer. Between single stack and double stack devices, single stack NC-NSFET offers faster switching at low operating voltages. Within a stack, nonuniformity in NS cross sections is found to influence device behavior. We also report the performance of NC-NSFETs in terms of key device design parameters, like channel length, thickness, and width of NS, and metal work function (WF), where, thinner NSs and metals with high WF provide significant enhancement in I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio. The results presented here can aid in the design, operation, and performance improvement of emerging NC-NSFET devices.

Hetero-Interfacial Thermal Resistance Effects on Device Performance of Stacked Gate-All-Around Nanosheet FET

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/ M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width ( ${W}_{NSH}$ ) and sheets stacking number ( ${N}$ ) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors.

Optimized Substrate for Improved Performance of Stacked Nanosheet Field-Effect Transistor

The recently proposed stacked nanosheet-field-effect transistor (SNSH-FET) is considered as a promising candidate for continued scaling with silicon. While using punchthrough-stopper-doped (or) ground-plane-doped silicon substrate (PTS-Si substrate) in which the top part of the substrate is doped heavily with the p-type (for nMOS) impurity to avoid punchthrough leakage between the source and the drain. The heavily doped p–n junction formed at the drain–substrate junction acts as a reverse-biased tunnel diode during ${V}_{{\text {DS}}}$ biasing, which leads to large substrate leakage current. We presented SuperSteep-Retrograde silicon substrate (SSR-Si substrate) configuration which reduces the tunneling current by increasing the tunnel barrier width and diminishing the peak electric field at the drain–substrate junction. The SSR-Si substrate is achieved by growing a lightly doped or undoped layer of silicon (SSR-buffer layer) on the PTS-doped substrate. The impact of SSR-buffer layer thickness is studied and the optimal thickness (12 nm) is presented. The vertically stacked channels’ configuration leads to position-dependent current densities in different channels due to position-dependent series resistance. Herein, we present nanosheet width optimization as a solution to achieve homogeneous current ratio between all the channels thereby resulting in better linearity performance. The self-heating and RF performance of the presented SSR-Si substrate is compared with the silicon-on-insulator (SOI) substrate. The results show that SSR-Si substrate can be a better substrate for SNSH-FET because of better self-heating performance.

Core Insulator Nanosheet Transistor and Structure Optimization to Improve Gate Electrostatic Characteristics.

This paper proposes the core insulator nano-sheet transistor structure for improved electrostatic characteristics by adding an oxidation process to the conventional Nano-sheet field effect transistor process. The additional insulated core improves the drain induced barrier lowering and the subthreshold slope properties by enhancing the gate controllability. The major advantage of the proposed structure is that it can be fabricated using the conventional nano-sheet field effect transistor process by simply adding another oxidation step. We compared the performance of our proposed device to that of FinFET and nano-sheet field effect transistor at sub 3 nm node using technology computer-aided design simulation. An optimal device structure including the oxide thickness and channel stacking is suggested with consideration for drive current, leakage and electrostatic characteristics.