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Abstract
Through-silicon via (TSV)-induced mechanical stress and electrical noise coupling effects on sub 5-nm node nanosheet field-effect transistors (NSFETs) were investigated comprehensively compared to fin-shaped FETs (FinFETs) using TCAD for heterogeneous 3D-ICs. TSV-induced channel length directional stress ( $S_{ZZ}$ ) predominantly causes variations of on-state current ( $\Delta I_{on}$ ). NSFETs exhibit the greater $\Delta I_{on}$ than FinFETs because electron velocities and densities in channels vary with respect to $S_{ZZ}$ in the same directions for NSFETs but do the opposite for FinFETs. Nevertheless, TSV-induced mechanical stress is negligible when TSV is farther than keep-out zone. Meanwhile, TSV signals can be coupled to operating devices through substrate and induce capacitive and back-bias noise coupling currents ( $I_{cap}$ , $I_{b-b}$ ). NSFETs exhibit the greater $\vert I_{cap}\vert /I_{on}$ than FinFETs because its wider source/drain (S/D) epitaxies form larger depletion capacitances between drain and punch-through stopper (PTS). On the other hand, the $\vert I_{b-b}\vert /I_{on}$ is smaller for NSFETs because its parasitic bottom transistor alleviates back-bias-induced potential barrier lowering. Furthermore, wide diameter of Cu of TSV increases $\vert I_{b-b}\vert /I_{on}$ only, but short rise time of TSV signals increases both $\vert I_{cap}\vert /I_{on}$ and $\vert I_{b-b}\vert /I_{on}$ . Unfortunately, conventional devices cannot satisfy criterion for analog applications ( $\vert I_{cap}$ , $I_{b-b}\vert /I_{on} %); therefore, a new strategy inserting bottom oxide (BOX) beneath the S/D with undoped PTS is suggested. The $\vert I_{cap}\vert /I_{on}$ for NSFETs decreases by undoped PTS, but not for FinFETs due to a remnant depletion capacitance between fin and PTS. The $\vert I_{b-b}\vert /I_{on}$ for NSFETs decreases remarkably due to completely blocked $I_{b-b}$ path, but FinFETs still have $I_{b-b}$ path under the fin. Therefore, NSFETs with BOX and undoped PTS are the most suitable for sub 5-nm node heterogeneous 3D-IC, especially in analog applications.
Highlights
Silicon fin-shaped field-effect transistors (FinFETs) have been used in the industry since the 22-nm node with excellent gate-to-channel controllability
Minor varies electrostatic potential in the PTS (VPTS) with respect to the DCu is observed at short trise. Both nanosheet FETs (NSFETs) and FinFETs do not satisfy the criterion for analog applications (|Icoupling|/Ion < 0.5%) at the short trise [16]
Through-silicon via (TSV)-induced mechanical stress effects and electrical noise coupling effects on sub 5-nm node n-type NSFETs were explored compared to FinFETs quantitatively
Summary
Silicon fin-shaped field-effect transistors (FinFETs) have been used in the industry since the 22-nm node with excellent gate-to-channel controllability. J. Jeong et al.: Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node NSFETs be linearly modulated by adjusting the NS channel width. In a via-middle TSV process, the final cooling cycle is known to determine the TSV-induced mechanical stress [17] Another effect is the electrical noise coupling between the TSVs and operating devices. TSV filling metal surrounded by a dielectric layer (liner) shares common substrate with devices, noise current can be injected into the devices through the substrate [18]–[21] This noise current can degrade the performance significantly in sensitive applications such as analog and RF circuits [20]. Sub 5-nm node FinFETs were compared quantitatively to determine which devices are more suitable for heterogenous 3D-ICs. the impacts of the TSV on channel stress and on-state current (Ion) was analyzed in terms of TSV locations. A new strategy to alleviate TSV-induced noise coupling current is suggested, and the most suitable devices for heterogeneous 3D-ICs are explored
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