Application of orthogonal experimental design for the interfacial reliability of Through-Silicon Vias structure

Abstract

Integrated circuits (ICs) undergo dimensional reduction and the functional unit of density dramatically increases, the reliability issue becomes more critical, especially with respect to three-dimensional (3D) silicon integration technology. Through-Silicon Vias (TSVs) technology is one of the most prominent feature used for interconnecting between chips. Since TSVs contain interfaces of heterogeneous materials with high CTE mismatch, large thermal stresses would appear at this place under temperature loading, often leading to mechanical failure. The mathematical model of thermal stress and the fracture failure modelling of Cu/SiO 2 interface in TSV using finite element method (FEM) with cohesive zone model was employed. The influence of the diameter and height of Cu, the thickness of SiO 2 and the pitch of TSVs array on stress of TSV was calculated by orthogonal experimental designs. And range analysis was also adopted to investigate the Cu/ SiO 2 interfacial reliability. The simulations reveal that the scalar stiffness degradation variable increased along with the diameter of Cu growing, but as the thickness of SiO 2 grew from 0.5µm to 1.5µm, there was a gradual decrease of the scalar stiffness degradation variable. The order of different structural parameters responsible for the TSV failure is: the diameter of Cu, the thickness of SiO 2 , the height of the via hole, and the pitch of TSV. A TSV sample was selected to calculate the failure of the annealing process using cohesive zone model. The results showd that the stress of Cu/SiO 2 interface was dominated by shear stress, and the failure mode of TSV was sliding mode failure.