Abstract
Grain boundary (GB) at the source/drain (S/D) epitaxy was investigated using fully-calibrated TCAD. Because the S/D epi is grown separately at the bottom and the NS channels, nanosheet field-effect transistors (NSFETs) have unwanted GB within the S/D epi which fully relaxes the channel stresses. This GB changes the doping profiles and the stress values, which thus degrade the DC performances. We focused on single GB with different inclined angles and positions. N-type NSFETs have similar DC performances regardless of the GB since the changes of doping and stress were small. P-type NSFETs suffer from DC performance degradations but different depending on the GB positions. As the GB splits the p-type S/D epi into two, lower S/D below the GB has tensile stress and upper S/D above the GB has compressive stress. Since tensile stress increases boron diffusivity, more boron dopants diffuse into the NS channels as the device has lower S/D region, thus suffering the short channel effects greatly. The device having upper S/D region loses the channel stress much, so it degrades the on-state performance. This study provides clear understanding of the GB effects of NSFETs.
Highlights
Silicon gate-all-around nanosheet field-effect transistors (NSFETs) have been introduced as one of the strong candidates to substitute FinFETs by achieving higher gateto-channel controllability and greater current drivability [1]
Other variation sources such as critical dimension for anisotropic etching source/drain (S/D) and middle-of-line [7] and parasitic bottom transistor induced by S/D over-etching [17]-[20] affect the variations of NSFETs greatly
We adopted advanced calibration to consider the doping profiles induced by stresses and grain boundary (GB) of Si and SiGe which were calibrated with experimental data [31]
Summary
Silicon gate-all-around nanosheet field-effect transistors (NSFETs) have been introduced as one of the strong candidates to substitute FinFETs by achieving higher gateto-channel controllability and greater current drivability [1]. Previous work analyzes the process variations between FinFETs and NSFETs in detail [4]-[16]. Because NS channel thickness (TNS) is determined by epitaxial growth instead of anisotropic etching for fin, TNS variation is negligible [1], [4], [5], and induces smaller DC performance variations than FinFETs. But other variation sources such as critical dimension for anisotropic etching source/drain (S/D) and middle-of-line [7] and parasitic bottom transistor induced by S/D over-etching [17]-[20] affect the variations of NSFETs greatly. In this work, we analyzed GB-induced DC performance variations of sub-3-nm n- and p-type NSFETs using fully-calibrated TCAD which considers the device structure and the experimental transfer curves at two different drain voltages (VDS) for fitting. Doping profiles and stress values of the devices, and identified the physical effects to the DC performance variations in detail
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