Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

N Aruna Kumari,P Prithvi

doi:10.1007/s12633-022-01695-7

Abstract

Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in sub-7-nm technology. This paper provides insights into the variations of DC FOMs for different geometrical configurations of the NSFET. In this script, the DC performance of 3D GAA NSFET is analyzed by varying the device's width and thickness. Moreover, the gate length is scaled from 20 nm to 5 nm to check for the device suitability for continuous scaling in logic applications. The thickness and width of each nanosheet are varied in the range of 5 to 9 nm and 10 to 50 nm, respectively, to analyze the performance dependency on the geometry of the device. The impact of geometry of NSFET on various DC performance metrics like transfer characteristics, sub-threshold swing (SS), on current (ION), off current (IOFF), switching ratio (ION/IOFF), threshold voltage (Vth), and drain induced barrier lowering (DIBL) are studied. On top of that, the device's electrical characteristics are analyzed for a wide range of temperatures from -43oC to 127oC to identify the temperature compensation point and is observed at VGS = 0.55 V and ID = 3.86 × 10-6 A. Furthermore, the vital process parameter, work function variations on transfer characteristics of the device is analyzed. Moreover, the analyses reveal that, for sub -7 nm, the NSFET is a potential device for high performance and suitable for logic applications.

Highlights

From the past five decades, the semiconductor industry has taken major steps in designing to improve the performance of semiconductor devices
DC characteristics are presented for Nanosheet Field Effect Transistor (NSFET). nanosheet thickness is varied in the range of 5 nm to 9 nm and width is varied from 10 nm to 50 nm to analyse the performance dependency on the geometry of NSFET
The detailed DC performance of 3D vertically stacked NSFET is analyzed by varying the thickness and width of the nanosheet

Summary

Introduction

From the past five decades, the semiconductor industry has taken major steps in designing to improve the performance of semiconductor devices. As a consequence of this, the lateral electric field from the source and drain starts affecting the channel in addition to the vertical electric field from the gate This phenomenon introduces the disadvantageous short channel effects (SCEs) in orthodox MOSFETs. As the gate length is decreasing the gate loses its control over the channel which gives scope for Short Channel Effects (SCEs) and leakage currents. For sub 7nm technology node and beyond the GAA nanosheet structures emerged as potential contenders for conventional FinFETs because of their excellent control on channel region and are successors of FinFETs due to better leakage control and high current drive capability. Compared to nanowire and FinFET structures, nanosheet FETs have shown superior electrostatic performance on channel [27].

Nsfet Structure And Simulation Procedure

Result

Impact on DC performance of NSFET with geometric variations

Impact of temperature and work function variations on NSFET

Conclusion