Impact of LER on Mismatch in Nanosheet Transistors for 5nm-CMOS

Abstract

In this paper, we have reported the impact of line edge roughness (LER) on the electrical characteristics of Nanosheet field effect transistors (NSFET). We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness in fin-type, non-planar MOSFETs. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet's sidewalls as well as its top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness contributes to a negligible mismatch in NSFET characteristics. The mismatch performance of NSFET is compared with that of the nanowire field effect transistor (NWFET) for 5nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER.