Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS

Chandan Kumar Jha,Anshul Gupta,Pritam Yogi,Reinaldo A Vega,Charu Gupta,Abhisek Dixit

doi:10.1109/jeds.2020.3026534

Chandan Kumar Jha, Anshul Gupta + Show 4 more

Open Access

https://doi.org/10.1109/jeds.2020.3026534

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Abstract

Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with smaller feature sizes. In this article, we have reported and compared the impact of LER on the electrical characteristics of NSFETs and nanowire field-effect transistors (NWFETs) for the sub-7nm technology node. We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness analysis at advanced CMOS technology nodes. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet’s sidewalls as well as top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness in NSFETs contributes to a negligible mismatch in threshold voltage and ON current. The mismatch performance of NSFET is compared with that of the NWFET for sub-7nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER. In addition to this, FETs with different channel doping modes such as inversion (IM) and Junction less (JL) mode have been compared for their matching performance against 3-D LER. It can be concluded from the results that IM FETs are more immune to 3-D LER as compared to JL FETs.

Highlights

Nanosheet field-effect transistors (NSFETs) have gained significant attention in recent days owing to its higher drive current and superior frequency response compared to FinFET and nanowire field-effect transistors(NWFETs) [1]–[5]
It is observed that with only sidewall roughness component, NSFET shows minimal or negligible mismatch in current and threshold voltage when compared to NWFET
Even when roughness is considered along all the sides of NS FET channel, the current mismatch is found to be lower in NSFET as compared to NWFET

Summary

INTRODUCTION

Nanosheet field-effect transistors (NSFETs) have gained significant attention in recent days owing to its higher drive current and superior frequency response compared to FinFET and nanowire field-effect transistors(NWFETs) [1]–[5]. JHA et al.: COMPARISON OF LER INDUCED MISMATCH IN NWFET AND NSFET FOR 5-nm CMOS edge roughness (GER) [23]. LER can induce variation in sheet thickness (Tfin), fin width (Dfin) of NSFET, and as well as in diameter (Dnw) of NWFET, which may result in a higher mismatch in threshold voltage (Vth), and drive current (Ion) in these devices [25]–[28]. Many papers reported analysis of LER induced mismatch on FinFET and NWFET based on 3-D LER models [20], [25]. Calibrated TCAD device model parameter values are listed, where ‘γ ’ represents the quantum potential model parameter, ‘WF’ represents metal gate work function, ‘C’ represents phonon scattering parameter, ‘δ’ represents surface roughness scattering parameter, and ‘vsat0’ represents the high-field saturation parameter.

MISMATCH IN NSFET AND NWFETS

CONCLUSION