Comparing bulk-Si FinFET and gate-all-around FETs for the 5 ​nm technology node

Abstract

In this paper, bulk CMOS finFET, horizontal gate-all-around (GAA) nanowire and nanosheet field-effect transistors are compared for the 5 ​nm technology node. The performance of these transistors and the circuits comprising them is assessed through 3-D technology computer-aided design (TCAD) simulations and circuit level SPICE simulations of BSIM compact models calibrated to the TCAD results, respectively. Full parasitic extraction is used on standard cell and static random access (SRAM) memory cell layouts to ensure accurate delays. The target of this work is a 5 ​nm technology node follow-on to an existing 7 ​nm predictive process design kit (PDK) in common academic use. Subthreshold slope, drain induced barrier lowering, gate-induced drain leakage and subthreshold current are compared for different gate lengths. Transistor performance is also compared for various raised source/drain lengths and low-k gate spacer widths. The gate-all-around field-effect transistors show better electrostatic performance as expected. However, the simulation results show that finFET devices will be adequate at the 5 ​nm node, should the GAA devices prove to be difficult to produce in high volume manufacturing.