Abstract
A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ </tex-math></inline-formula> ) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.
Highlights
Three-dimensional (3D) fin field-effect transistors (FinFETs) have been successfully developed for the manufacturing of high-volume integrated circuits (IC) from 22 nm to 5 nm node because of their better channel electrostatic control and higher driving ability compared to those of conventional planar devices [1]–[3]
In order to satisfy the demand for the higher Weff/footprint ratio and better gate controllability to suppress short channel effects (SCEs), vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FET) has been regarded as one of the most promising candidates to replace FinFET in sub-3nm technology nodes [4]–[7]
Benefiting from the high ground plane (GP) doping concentration of subfin for suppressing PEC, the total trend of Id-Vg curves from sub-threshold to saturated region are stable as TN increases
Summary
Three-dimensional (3D) fin field-effect transistors (FinFETs) have been successfully developed for the manufacturing of high-volume integrated circuits (IC) from 22 nm to 5 nm node because of their better channel electrostatic control and higher driving ability compared to those of conventional planar devices [1]–[3]. As the technology nodes scale down to 3 nm and beyond, many challenges, such as deteriorated electrostatic integrity, irresistible short-channel effects (SCEs), degraded device performance and large process variability, appear for the FinFET device. In order to satisfy the demand for the higher Weff/footprint ratio and better gate controllability to suppress short channel effects (SCEs), vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FET) has been regarded as one of the most promising candidates to replace FinFET in sub-3nm technology nodes [4]–[7]. Higher the GP doping concentration in the scaled GAA NSFET may results in other issues, such as band-to-band tunneling (BTBT) induced serious gate-induced drain leakage (GIDL) effect [9], carrier velocity degradations and
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