Process Flow Modelling and Characterisation of Stacked Gate-All-Around Nanosheet Transistors

Abstract

A fabrication process of stacked n-type gate-all-around (GAA) triple nanosheet (NS) field-effect transistors (FETs) is modelled by the 3D Victory Process (TCAD by Silvaco). The modelling confirms that the NS FET process flow is highly compatible with the FinFET fabrication. To verify the accuracy of the process modelling, carrier transport in the NS FET is simulated by the 3D Victory Device using quantum corrected drift-diffusion. Simulated I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> -V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> characteristics at drain biases of 0.05 V and 0.7 V are in a very good agreement with experimental data, including the sub-threshold region. The 1st NS channel provides the largest contribution to current density, while additional channels still contribute by a good increase to current density. The stacked GAA NS FETs are proved to be the cost-effective and performance-fitting solution for the sub-5 nm CMOS technology nodes.