A Comprehensive Investigation of Vertically Stacked Silicon Nanosheet Field Effect Transistors: an Analog/RF Perspective

Abstract

In this article, the analog/RF performance of n-channel vertically stacked gate all around (GAA) silicon nanosheet field effect transistors (Si-NSFETs) are investigated using 3-D TCAD simulations. The influence of gate length (LG) scaling, nanosheet width (WNS) and spacing between the nanosheets on the analog/RF performance of vertically stacked GAA Si-NSFET with two nanosheets are explored. The 3-D TCAD simulations indicates that reducing LG from 20 nm to 12 nm results in the improvement of RF performance in terms of increased gm (transconductance), drive current, fT (cut off frequency), fmax (maximum oscillation frequency) and degradation of analog performance in terms of reduced intrinsic gain. 3-D TCAD simulations also shows that increasing the WNS from 10 nm to 18 nm leads to the enhancement of gm and drive current, does not affect the fT and degrades the intrinsic gain due to the increase of drain conductance and gate capacitance. It is also observed that the spacing between the nanosheets does not have any significant impact on analog/RF performance of vertically stacked GAA Si-NSFETs. Consequently, the vertically stacked GAA Si-NSFETs with lower LG and higher WNS will be more suitable to realize both flash memory and dynamic random access memory (DRAM) for improved performance owing to their better RF performance.