TID Circuit Simulation in Nanowire FETs and Nanosheet FETs

Jongwon Lee,Myounggon Kang

doi:10.3390/electronics10080956

Abstract

In this study, the effects of the total ionizing dose (TID) on a nanowire (NW) field-effect transistor (FET) and a nanosheet (NS) FET were analyzed. The devices have Gate-all-around (GAA) structure that are less affected by TID effects because GAA structures have better gate controllability than previously proposed structures, such as planar MOSFETs and FinFETs. However, even for GAA devices with the same channel cross-sectional area and equivalent oxide thickness, structural differences can exist, which can result in different tolerances of TID effects. To observe the device and circuit operation characteristics of these GAA devices with structural differences, n-type and p-type devices were designed and simulated. The circuit simulation according to TID effects was conducted using Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. The NS-FET generated more VT shift than the NW-FET because the NS-FET had a wider gate oxide area and channel circumference, resulting in more interface hole traps. The abnormal VT shift leads to causing unstable circuit operation and delays. Therefore, it was confirmed that the ability of the NW-FET to tolerate TID effects was better than that of the NS-FET.

Highlights

Semiconductor devices are widely used in many areas, such as aerospace applications, radiation therapy, and nuclear reactors, where accumulative damage caused by high-energy radiation particles can be a significant threat
The Berkeley short-channel insulated-gate FET model (BSIM)–common multi-gate (CMG) model parameters were used instead of various other commercially available BSIM model parameters to extract the device characteristics for total ionizing dose (TID) effects. This is because other models, such as BSIM 4, are based on planar MOSFETs, so it is not easy to adjust a graph between simulation data values and BSIM 4 parameter values in 3D structure devices
The larger number of holes trapped in the NS-field-effect transistor (FET) device was caused by the wider gate oxide area

Summary

Introduction

Semiconductor devices are widely used in many areas, such as aerospace applications, radiation therapy, and nuclear reactors, where accumulative damage caused by high-energy radiation particles can be a significant threat. This is to maintain the same equivalent oxide thickness and increase the thickness of the gate oxide [8] For this reason, the gate oxide area of the gate-all-around (GAA) structure is wider than before, which is necessary to analyze the TID effects. The gate oxide area of the gate-all-around (GAA) structure is wider than before, which is necessary to analyze the TID effects Because these radiation-induced phenomena tend to recover slightly within a short time after their occurrence, analysis by measurement has many difficulties [9]. The extraction of TID effects characteristic of irradiated devices was performed using Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters

Method of Analyzing TID Effects

Compact Modeling Using BSIM–CMG Model Parameters

Findings

Conclusions