Abstract
In this study, we analyzed the total ionizing dose (TID) effect characteristics of p-type FinFET and Nanowire FET (NW-FET) according to the structural aspect through comparison of the two devices. Similar to n-type devices, p-type NW-FETs are less affected than FinFETs by the TID effect. For the inverter TID circuit simulation, both n- and p-types of FinFET and NW-FET were analyzed regarding the TID effect. The inverter operation considering the TID effect was verified using the Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. In addition, an inverter circuit composed of the NW-FET exhibited a smaller change by the TID than that of an inverter circuit composed of the FinFET. Therefore, the gate controllability of the gate-all-around (GAA) device had an excellent tolerance to not only short-channel effects (SCE) but also TID effects.
Highlights
Radiation hardening on semiconductor devices is a critical issue in various fields including radiation therapy, space, and nuclear reactor processes
total ionizing dose (TID) simulations of a FinFET and Nanowire FET (NW-FET) were carried out to analyze the element with a larger TID effect, according to the device structural part
It is shown by introducing the GAA structure, that the higher the gate controllability, the more the TID effect can be suppressed in the oxide region
Summary
Radiation hardening on semiconductor devices is a critical issue in various fields including radiation therapy, space, and nuclear reactor processes. TID simulations of a FinFET and NW-FET were carried out to analyze the element with a larger TID effect, according to the device structural part. Despite the larger oxide area of the NW-FET than the FinFET, the VT did not change significantly, and the device appeared to be more resistant to radiation. It is shown by introducing the GAA structure, that the higher the gate controllability, the more the TID effect can be suppressed in the oxide region. The FinFET and NW-FET affected by the TID were extracted using a Berkeley short-channel insulatedgate FET (BSIM) common multi-gate (CMG) and applied to an inverter circuit to perform the simulation
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