CMOS Power Amplifier Research Articles

A Linear CMOS Power Amplifier With Efficiency-Optimized Transformer Matching

A 29.5-GHz power amplifier (PA) with a codesigned transformer-based matching network and a second harmonic control network is presented here. The efficiency of the transformer is well studied, and an accurate analytical solution to a high-efficiency transformer has been proposed. Guiding by it, a high-efficiency 1:2 transformer has been designed. A series <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> network has been added between the drain and the source as a second harmonic control network. Due to the codesign, the cost of the harmonic control network is negligible. The PA achieves a 3-dB gain bandwidth from 26.9 to 33.2 GHz (21%). The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {1\, dB}}$ </tex-math></inline-formula> exceeds 16.5 dBm with power added efficiency (PAE) beyond 27% from 27.5 to 30 GHz. At 29.5 GHz, the proposed PA achieves a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {1 \,dB}}$ </tex-math></inline-formula> of 17.4 dBm with 30% PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula> of 17.8 dBm with the peak PAE of 30.7%.

Support Vector Machine-Based Model for 2.5-5.2 GHz CMOS Power Amplifier.

A power amplifier (PA) is the core module of the wireless communication system. The change of its specification directly affects the system’s performance and may even lead to system failure. Furthermore, change in the PA specification is closely related to changes in temperature. To study the influence of PA specification change on the system, we used a support vector machine (SVM) to model the temperature characteristics of PA. For SVM modeling, the question of how much experimental data should be used for modeling to meet the requirements is a constant problem. To address this issue, we investigate the effect of different amounts of training data on the modeling of SVM models. The results show that only 75% of the experimental data needs to be used in the modeling process to satisfy the modeling requirements of the SVM model. The number of measurement points required in the PA specification degradation experiment can be reduced by 25%. The results of this paper serve as a guide for planning the number of experimental measurement points and reducing the measurement cost and measurement time.

Load-Modulation-Based IMD3 Cancellation for Millimeter-Wave Class-B CMOS Power Amplifiers Achieving EVM &lt; 1.2%

This letter presents a novel load-modulation-based 3rd-order intermodulation distortion (IMD3) cancellation technique for class-B CMOS power amplifiers (PAs). In a class-B PA, the IMD3 generated by the 3rd-order transconductance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m3}$ </tex-math></inline-formula> ) and the gain compression have opposite signs, and thus, they can cancel each other at specific bias and loading conditions. The proposed Doherty topology allows adjusting the gain compression by modulating the effective loading, facilitating IMD3 cancellation over the entire load modulation region. The proposed approach is verified using a 28 GHz 40 nm CMOS series-Doherty PA (DPA) topology. The experimental result demonstrates 10/17 dB IMD3 improvement compared to class-B/DPA operation. Without using any digital pre-distortion, the measured EVM of the proposed technique for a 50 MHz 64-QAM OFDM signal with 8.9 dBm average output power is −38.7 dB (1.2%), which is 5.7/11 dB better than a standard class-B/DPA operation.

A Compact Transformer-Based E-Band CMOS Power Amplifier with Enhanced Efficiencies of 15.6% PAE1dB and 6.5% PAE at 6 dB Power Back-Off

This paper presents a compact E-band power amplifier (PA) implemented in a 40 nm CMOS process. The neutralization technique is adopted to improve reverse isolation, stability and power gain. The linearity of the PA is improved by operating the output stage in the deep class-AB region. Transformer-based matching networks (TMNs) are used for impedance transformation, and optimized for output power and efficiency. At 81 GHz, the presented PA achieves a maximum output 1 dB compressed power (P1dB) of 11.2 dBm and a saturated output power (Psat) of 12.7 dBm with 1 V supply. The power-added efficiencies at P1dB (PAE1dB) and 6 dB power back-off (PBO) are 15.6% and 6.5%, respectively.

Ku-Band CMOS Power Amplifier with Three-Stack Power Stage to Enhance Output Power and Efficiency

In this study, we proposed a power amplifier structure with improved efficiency while securing high output power. First, the characteristics of the common-source and stack structures were investigated. In particular, the output power and output impedance characteristics of the stack structure were analyzed compared with the common-source structure. A common-source structure was applied to the driver stage to minimize dc power consumption, and a stack structure was applied to the power stage to ensure high output power. In order to verify the proposed structure, a Ku-band power amplifier was designed using the 65-nm RF CMOS process that provides nine metal layers. At the operating frequency of 15 GHz, saturation output power and maximum power-added efficiency were confirmed to be 22.1 dBm and 17.2%, respectively.

공통 소스 트랜지스터의 Self-Body-Biasing을 통해 선형성이 향상된 2.45 GHz CMOS 전력증폭기의 설계

This study introduces the design of an RF CMOS power amplifier based on a cascode powercell. self-body-biasing (SBB) of common source (CS) transistors (TRs) was proposed to improve the nonlinearity of power amplifiers. Accordingly, an analysis of the linearization principle of SBB was performed through simulation. The SBB technique is configured by inserting a 4 kΩ resistor between the body and the drain of the CS TRs. Accordingly, using the SBB to the CS TRs could achieve the effect of reducing the third-order intermodulation distortions (IMD3) by changing the third-order transconductance (gm3). Moreover, an effect of reducing AM-PM distortions could be achieved by securing a voltage condition in which the CG TRs could operate in a saturation region, which reduces the variation of parasitic capacitances at the output terminal.

Broadband Millimeter-Wave 5G Power Amplifier Design in 22 nm CMOS FD-SOI and 40 nm GaN HEMT

Three millimeter-wave (mm-Wave) power amplifiers (PAs) that cover the key 5G FR2 band of 24.25 to 43.5 GHz are designed in two different state-of-the-art device technologies and are presented in this work. First, a single-ended broadband PA that employs a third-order input matching network is designed in a 40 nm GaN/SiC HEMT (High Electron Mobility Transistor) technology. Good agreement between the measurement and post-layout parasitic extracted (PEX) electromagnetic (EM) simulation data is observed, and it achieves a measured 3-dB BW (bandwidth) of 18.0–40.3 GHz and &gt;20% maximum PAE (power-added-efficiency) across the entire 20–44 GHz band. Expanding upon this measured design, a differential broadband GaN PA that utilizes neutralization capacitors is designed, laid out, and EM simulated. Simulation results indicate that this PA achieves 3-dB BW 20.1–44.3 GHz and maximum PAE &gt; 23% across this range. Finally, a broadband mm-Wave differential CMOS PA using a cascode topology with RC feedback and neutralization capacitors is designed in a 22 nm FD-SOI (fully depleted silicon-on-insulator) CMOS technology. This PA achieves an outstanding measured 3-dB BW of 19.1–46.5 GHz and &gt;12.5% maximum PAE across the entire frequency band. This CMOS PA as well as the single-ended GaN PA are tested with 256-QAM-modulated 5G NR signals with an instantaneous signal BW of 50/100/400/9 × 100 MHz at a PAPR (peak-to-average-power ratio) of 8 dB. The data exhibit impressive linearity vs. POUT trade-off and useful insights on CMOS vs. GaN PA linearity degradation against an increasing BW for potential mm-Wave 5G applications.

Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems

A two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage was provided and simulated. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband matching. The shunt peaking topology in a common source configuration is adopted at the second stage to enhance the power gain. The postlayout simulation is performed using the TSMC 65 nm CMOS process operating in a frequency band of 3.1 GHz to 10.6 GHz. The postlayout simulation results indicate that a high flat gain of approximately 22.8 ± 1.2 dB, small group delay variation of ±50 ps, and good input and output matching of less than −10 dB are achieved over the desired working band. Moreover, a saturated output power of 10 dBm and maximum power-added efficiency (PAE) of 29.5% is achieved at 6 GHz. The proposed PA consumes the low power of 15.5 mW from 1.2 V supply voltage.

A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications

This paper presents a novel dual mode configurable and tunable power amplifier (PA) that achieves a wide-bandwidth and high gain across a operational frequency spectrum of 20 to 30 GHz. The proposed PA used two-stage tunable PA which can be configured as a tunable synchronous mode or tunable stagger-tuned mode PA. PA is implemented by using a distortion-free varactor at the input and output tank of PA. The designed PA includes a high-Q CMOS active inductor (CAI) which provides a widely tunable output matching network. The resistive feedback is used for self-biasing in the designed PA which helps to enhance the linearity, stability of common source (CS) amplifier. The inter-stage impedance matching network consists of shunt and series resonance circuits are employed for maximum power added efficiency (PAE). Furthermore, the capacitive coupled reuse technique is implemented in each stage between the cascaded transistor to reduce the power consumption. A proposed PA is designed using a 65 nm CMOS technology. A measured power gain at the synchronous operation of PA is 28.4 ±0.5 dB with 1.31 GHz bandwidth while power gain at staggered operation is 22.1 ±0.5 dB with 3.71 GHz bandwidth. The measured saturated power (Psat) is 14.21 dBm and the noise figure (NF) is 5.2 dB. The group delay (GD) variation for staggered operation is 57 ±10 ps from 20-30 GHz. A proposed PA exhibits good linearity (IIP3) of 14.5 dBm and PAE is 47.5 % at 24 GHz. The power consumption of a designed PA is 48.56 mW with a supply voltage of 1.2 V.

A Compact 140-GHz CMOS Power Amplifier With 10.5-dBm Output Power and 27.6-dB Power Gain Supporting up to 128-QAM Modulation

A compact 140 GHz power amplifier (PA) with employed multi-layer stacked transformer (MLST) matching network is implemented in a 65-nm CMOS process. The employed MLST matching network adopts two metal layers as the primary coil and one single layer as the secondary coil to increase the coupling factor and decrease the insertion loss (IL) of the matching network at D-band frequency range. Besides, a gain-boosting unit is further introduced in the first stage of the PA to enhance the power gain. The proposed 140 GHz PA achieves a measured PAE of 6.9%, a Psat of 10.5 dBm and an OP1dB of 7.03 dBm with a maximum power gain of 27.6 dB when the gain-boosting unit turns off. By turning on the gain-boosting unit, the power gain managed to increase from 27.6 dB to 31 dB with stability. Furthermore, modulation measurement shows that the proposed D-band PA supports 24 Gb/s 64-QAM and 11.2 Gb/s 128-QAM modulated signals with error vector magnitudes (EVM) of -23.1 dB/-22.87 dB at the output power of 7 dBm, respectively. The core chip area and dc power consumption of the PA are only 0.0275 mm and 170 mW.

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

This paper presents a bias modulation linearization technique for a 919-923MHz CMOS power amplifier which employs driver voltage modulation and main amplifier split bias. Through the proposed linearization technique, it is observed that the peak third-order intercept point (OIP3) across the output power is shifting according to the bias conditions of the split-bias power amplifier (SBPA). The third-order transconductance (gm₃) terms are suppressed at the output by phase cancellation achieved by optimization of the bias voltages of the PA. A high dynamic range bias circuit is integrated at the driver and split main to enhance the linearity of the CMOS PA, eradicating the need for pre-distortion linearizers. The two-stage SBPA is designed and fabricated in a 180 nm CMOS process with six-metal layers and a chip size of 1.820 x 1.771 mm² to operate at the supply voltage of 3.3 V. The bias voltages of both driver and split main stages are varied from 0 V to 2.0 V with a linear step size of 0.2 V. The proposed SBPA delivers a saturated output power (P_out) of 27 dBm with maximum power-added efficiency (PAE) of 44.4 % and peak OIP3 of 39 dBm. A maximum linear P_out of 21 dBm with 29 % PAE is achieved at an adjacent channel leakage ratio (ACLR) of -30 dBc and 4 % error vector magnitude (EVM), satisfying the LoRa specifications.

A 54–68 GHz Power Amplifier With Improved Linearity and Efficiency in 40 nm CMOS

This brief presents a 54–68 GHz two-stage power amplifier (PA) with linearity and efficiency enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded common-source (CS) structure with a shunt RC feedback to maximize the gain and minimize the DC power consumption to boost the linearity and efficiency, while the second stage is a cascode structure with two built-in linearizers to enhance the linearity much further. Based on the proposed structure, the fabricated PA exhibits measured output of 1-dB compression point, saturated output power, power added efficiency (PAE) and AM-PM distortion of +14 dBm, +15 dBm, 20% and 8 degrees, respectively. In addition, the proposed CMOS PA achieves high and flat power gain of 14 dB with ripple less than 1.5 dB through the operating 54—68 GHz frequency band while consuming only 110 mW.

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

In this study, a differential power amplifier (PA) with a high gain of over 30 dB by configuring a three-stage common source unit amplifier was designed. To ensure the stability of the high-gain differential PA, the analysis to apply the capacitive neutralization method to the differential common source PA was conducted. From the analysis, the required neutralized capacitance was quantitatively calculated from the estimated parasitic components of a power cell used in the PA. To verify the feasibility of the proposed optimization technique, a Ka-band PA was designed with a 65 nm RFCMOS process. The measurement results showed a gain of 30.7 dB. The saturated output power was measured as 16.1 dBm, maximum power-added efficiency (PAE) was 29.7%, and P1dB was 13.1 dBm.

A 21.6dBm CMOS power amplifier using a compact high-k output transformer for X-band application

CMOS power amplifier (PA) has advantages in power consumption and integration, while the lower operating voltage limits its output power. An area efficient power combiner needs to be designed to improve the output power of CMOS PA. An X-band integrated PA using 65-nm CMOS bulk technology was presented in this work. The whole PA consists of two differential stages: a one-way drive amplifier and a two-way main amplifier. By employing a compactly designed high-k output transformer, the CMOS PA occupied a small core-area of 0.47×0.57mm2, and delivered 21.6 dBm of measured saturated output power with 23.6% of power-added efficiency at 10 GHz from a 1.2-V power supply. Simultaneously, this PA can operate well in 8∼15 GHz wideband.

A 1.7-to-2.7GHz 35–38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-Distorter (DAAPD) Reconfigurable Linearization Technique

This brief presents a CMOS power amplifier (PA) employing a digitally-assisted analog pre-distorter (DAAPD) reconfigurable linearization technique to reduce the back-off output power (PBO) for multiband operation. The proposed DAAPD optimizes the interstage load impedance between the driver and the main stage by changing the transconductance of the driver amplifier and its active load. We also utilize the DAAPD to optimize the PA when subjected to process-voltage-temperature (PVT) variations. Fabricated in 130-nm CMOS, the DAAPD-PA operates from 1.7 to 2.7 GHz with a 3 dB back-off output power efficiency of 35% to 38% while fulfilling the stringent adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of a 20-MHz 16-QAM LTE signal. With a continuous wave (CW) signal, the DAAPD-PA achieves a maximum output power of 27 to 28 dBm across frequencies of interest with supply headroom of 3.3 V. Finally, the DAAPD-PA covers 20 LTE bands with reduced back-off output power.

Experimentally investigating the performance degradations of the CMOS PA at different temperatures

To investigate the temperature dependency of the specifications for Power Amplifiers (PAs), the performance degradations of an IC PA under different temperature conditions are investigated experimentally. The experimental results show that the performance degradations of the PA are sensitive to temperature changes. The main reasons for these degradations are discussed and analyzed in this paper. The research performed in the study provides another angle to handle the practical working environments rather than the extreme cases as the reliability study.

A 23 dBm Gain Shaping Stacked Power Block CMOS Power Amplifier Achieving 36% PAE

This paper introduces a design methodology that reduces the fundamental trade-off between linearity and power added efficiency (PAE) in CMOS power amplifier (PA). In our work, a stacked power block (SPB) has been proposed to mitigate the effect of gate–source capacitance (Cgs), thus linearizing the PA. Each stage is biased independently to shape the gain profile, either to be in the expanded mode or in the compressed mode, in which once combined it delivers a flat gain response and confirming the linearity performance. Efficient PI input and output matching networks are proposed to ensure no further distortion, once connected to the 50 Ω source and load. The PA achieves input and output return losses of less than −10 dB from 2.40 to 2.50 GHz. At the center frequency of 2.45 GHz, the SPB-PA achieves a gain of 10 dB and it is unconditionally stable. The proposed gain shaping linearization technique delivers a maximum linear output power (Poutlinmax) of 19.8 dBm with only 3.3 dB back-off from maximum output power (Poutmax) of 23.1 dBm. The SPB-PA meets the WLAN specification with linear PAE of 30% and peak PAE of 36.1%. The proposed SPB-PA reduces the fundamental trade-off between linearity and efficiency. Integration of this PA in wireless SoC shall reduce the chip’s overall power consumption.

A 6 GHz Integrated High-Efficiency Class-F−1 Power Amplifier in 65 nm CMOS Achieving 47.8% Peak PAE

This paper reports a “single-transistor” Class-F−1 power amplifier (PA) in 65 nm CMOS, which operates at the microwave center frequency of 6 GHz. The PA is loaded with a Class-F−1 harmonic control network, employing a new “parasitic-aware” topology deduced using a novel iterative algorithm. A dual-purpose output matching network is designed, which not only serves the purpose of output impedance matching, but also reinforces the harmonic control of the Class-F−1 harmonic network. This proposed PA yields a peak power-added efficiency (PAE) of 47.8%, which is one of the highest when compared to previously reported integrated microwave/millimeter-wave PAs in CMOS and SiGe technologies. The amplifier shows a saturated output power of 14.4 dBm along with an overall gain of 13.8 dB.

매칭된 캐스코드 전력 셀 기반 K-/Ka-대역 CMOS 전력 증폭기

This study proposes a K-/Ka-band CMOS power amplifier (PA) with a matched cascode power cell. Interstage inductors are introduced between the common source (CS) and common gate (CG) transistors to achieve high power gain and high reverse isolation of the PA. Cold FETs are configured with interstage inductors to reduce the phase distortion of the PA. The input and output matching networks of the PA are designed as broadside-coupled transformers to obtain a high coupling coefficient and low insertion loss. The proposed PA is fabricated using a 65 nm RF CMOS process, whose chip dimensions are 0.99 mm × 0.57 mm. The device achieves a saturated output power of 19~21 dBm, power-added efficiency of 32~37 %, and power gain of 6.7~7.7 dB in a frequency range of 24~28 GHz. The linear power values for the IMD &lt; −30 dBc are in the range of 12.5~15 dBm in a frequency range of 24~28 GHz.

Design of a K-Band High-Efficiency Power Amplifier in 45 nm SOI CMOS Technology

This paper presents a high efficiency K-band CMOS power amplifier (PA) in GlobalFoundries (GF) 45 nm SOI CMOS technology for 5 G applications. Compared with an ordinary two-stage PA, the PA uses a current-reused technique to enhance the power gain and efficiency within the frequency band. The resistance feedback structure of the power output stage improves the gain flatness and the output bandwidth, and reduces the matching components. The simulation results show that the output power (Pout) is more than 21.6 dBm from 18 to 27 GHz, while the small signal gain (S21) is more than 30.6 dB, the output 1 dB compression point (OP1dB) is 19.8 dBm and power-added efficiency (PAE) is 36.8%. With a 64-QAM LTE signal with 20-MHz bandwidth, adjacent channel leakage ratio (ACLR) is −31.2 dBc and the error vector amplitude(EVM) is less than − 26.7 dB at an average output power of 10.9 dBm. The chip area with pads is 0.75mm2, and consumes 15.1 mW from 2.4 V.