A 1.7-to-2.7GHz 35–38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-Distorter (DAAPD) Reconfigurable Linearization Technique

Abstract

This brief presents a CMOS power amplifier (PA) employing a digitally-assisted analog pre-distorter (DAAPD) reconfigurable linearization technique to reduce the back-off output power (PBO) for multiband operation. The proposed DAAPD optimizes the interstage load impedance between the driver and the main stage by changing the transconductance of the driver amplifier and its active load. We also utilize the DAAPD to optimize the PA when subjected to process-voltage-temperature (PVT) variations. Fabricated in 130-nm CMOS, the DAAPD-PA operates from 1.7 to 2.7 GHz with a 3 dB back-off output power efficiency of 35% to 38% while fulfilling the stringent adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of a 20-MHz 16-QAM LTE signal. With a continuous wave (CW) signal, the DAAPD-PA achieves a maximum output power of 27 to 28 dBm across frequencies of interest with supply headroom of 3.3 V. Finally, the DAAPD-PA covers 20 LTE bands with reduced back-off output power.