Abstract
Three millimeter-wave (mm-Wave) power amplifiers (PAs) that cover the key 5G FR2 band of 24.25 to 43.5 GHz are designed in two different state-of-the-art device technologies and are presented in this work. First, a single-ended broadband PA that employs a third-order input matching network is designed in a 40 nm GaN/SiC HEMT (High Electron Mobility Transistor) technology. Good agreement between the measurement and post-layout parasitic extracted (PEX) electromagnetic (EM) simulation data is observed, and it achieves a measured 3-dB BW (bandwidth) of 18.0–40.3 GHz and >20% maximum PAE (power-added-efficiency) across the entire 20–44 GHz band. Expanding upon this measured design, a differential broadband GaN PA that utilizes neutralization capacitors is designed, laid out, and EM simulated. Simulation results indicate that this PA achieves 3-dB BW 20.1–44.3 GHz and maximum PAE > 23% across this range. Finally, a broadband mm-Wave differential CMOS PA using a cascode topology with RC feedback and neutralization capacitors is designed in a 22 nm FD-SOI (fully depleted silicon-on-insulator) CMOS technology. This PA achieves an outstanding measured 3-dB BW of 19.1–46.5 GHz and >12.5% maximum PAE across the entire frequency band. This CMOS PA as well as the single-ended GaN PA are tested with 256-QAM-modulated 5G NR signals with an instantaneous signal BW of 50/100/400/9 × 100 MHz at a PAPR (peak-to-average-power ratio) of 8 dB. The data exhibit impressive linearity vs. POUT trade-off and useful insights on CMOS vs. GaN PA linearity degradation against an increasing BW for potential mm-Wave 5G applications.
Highlights
Output power, frequency performance, size, and cost are inherent characteristics in every technology
Thanks to the thicker process layers and their semi-insulating substrates, III-V technologies provide better low-loss on-chip passives, which is crucial for the high Q needed to achieve great power efficiencies and on-chip EM structures
In the CMOS FD-SOI technology, power-added efficiency (PAE) and POUT load-pull simulations are performed in Cadence Spectre
Summary
Frequency performance, size, and cost are inherent characteristics in every technology. The GaN technology used in this work is HRL Laboratories’ T3 40 nm GaN HEMT (High Electron Mobility Transistor) technology on a SiC substrate, which achieves VBR of 50 V, fT of 220 GHz and fMAX of 400 GHz with a knee voltage of ~2 V, and ID,MAX of ~1.6 A/mm [4]. This work will use Global Foundries’ 22FDX technology, which is a 22 nm FD-SOI (fully depleted SOI) CMOS process to design a differential cascode mm-Wave broadband PA Devices in this technology achieve lower off-state leakage current due to the buried oxide layer and a fully depleted channel [5]. TThhiiss tteecchhnniiqquuee hhaass bbeeeenn eexxpplloorreedd iinn mmaannyypprreevviioouusswwoorrkkss[[88,,99]]aannddtthhuusswwiillllnnoottbbeeddiiss-cussed in deettaaiillhheerreebbuuttwweewwililllininstsetaedadjujustspt rporvoivdiedae barbierfierfevreievwie.wF.roFmromthethMeSMGSeGqueaqtuioantainond athnedstmhealslm-saiglln-sailgmnaoldmeloodfeal oMf aOMSFOESTF, EfoTr, afodriaffedrieffnetrieanl tpiaalirpwairithwiathneaunteraultirzaaltiizoantiocancpaapcaitcoirtoCrxC, xE, qEuqautaiotinon(1()1c)acnanbbeeddeerirviveeddwwhheerereththeeppaarraassititiiccggaatteettooddrraaiinn capacitance, Cggdd,, can be reduced by adding the neutralization capacitor Cxx,, aanndd tthhuuss caann increase the MSG of a differential amplififier [8,9]
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