A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications

Abstract

This paper presents a novel dual mode configurable and tunable power amplifier (PA) that achieves a wide-bandwidth and high gain across a operational frequency spectrum of 20 to 30 GHz. The proposed PA used two-stage tunable PA which can be configured as a tunable synchronous mode or tunable stagger-tuned mode PA. PA is implemented by using a distortion-free varactor at the input and output tank of PA. The designed PA includes a high-Q CMOS active inductor (CAI) which provides a widely tunable output matching network. The resistive feedback is used for self-biasing in the designed PA which helps to enhance the linearity, stability of common source (CS) amplifier. The inter-stage impedance matching network consists of shunt and series resonance circuits are employed for maximum power added efficiency (PAE). Furthermore, the capacitive coupled reuse technique is implemented in each stage between the cascaded transistor to reduce the power consumption. A proposed PA is designed using a 65 nm CMOS technology. A measured power gain at the synchronous operation of PA is 28.4 ±0.5 dB with 1.31 GHz bandwidth while power gain at staggered operation is 22.1 ±0.5 dB with 3.71 GHz bandwidth. The measured saturated power (Psat) is 14.21 dBm and the noise figure (NF) is 5.2 dB. The group delay (GD) variation for staggered operation is 57 ±10 ps from 20-30 GHz. A proposed PA exhibits good linearity (IIP3) of 14.5 dBm and PAE is 47.5 % at 24 GHz. The power consumption of a designed PA is 48.56 mW with a supply voltage of 1.2 V.