매칭된 캐스코드 전력 셀 기반 K-/Ka-대역 CMOS 전력 증폭기

Abstract

This study proposes a K-/Ka-band CMOS power amplifier (PA) with a matched cascode power cell. Interstage inductors are introduced between the common source (CS) and common gate (CG) transistors to achieve high power gain and high reverse isolation of the PA. Cold FETs are configured with interstage inductors to reduce the phase distortion of the PA. The input and output matching networks of the PA are designed as broadside-coupled transformers to obtain a high coupling coefficient and low insertion loss. The proposed PA is fabricated using a 65 nm RF CMOS process, whose chip dimensions are 0.99 mm × 0.57 mm. The device achieves a saturated output power of 19~21 dBm, power-added efficiency of 32~37 %, and power gain of 6.7~7.7 dB in a frequency range of 24~28 GHz. The linear power values for the IMD < −30 dBc are in the range of 12.5~15 dBm in a frequency range of 24~28 GHz.