Gate Oxide Thickness Research Articles

Retrograde p-Well for 10-kV Class SiC IGBTs

In this paper, we propose the use of a retrograde doping profile for the p-well for ultrahigh voltage (>uexcl;10 kV) SiC IGBTs. We show that the retrograde p-well effectively addresses the punchthrough issue, whereas offering a robust control over the gate threshold voltage. Both the punchthrough elimination and the gate threshold voltage control are crucial to high-voltage vertical IGBT architectures and are determined by the limits on the doping concentration and the depth that a conventional p-well implant can have. Without any punchthrough, a 10-kV SiC IGBT consisting of retrograde p-well yields gate threshold voltages in the range of 6–7 V with a gate oxide thickness of 100 nm. Gate oxide thickness is typically restricted to 50–60 nm in SiC IGBTs if a conventional p-well with $1 \times 10^{17}$ cm−3 is utilized. We further show that the optimized retrograde p-well offers the most optimum switching performance. We propose that such an effective retrograde p-well, which requires low-energy shallow implants and thus key to minimize processing challenges and device development cost, is highly promising for the ultrahigh-voltage (>10 kV) SiC IGBT technology.

Accurate Threshold Voltage Reliability Evaluation of Thin Al2O3 Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses.

Few-layer black phosphorus (BP) has attracted significant interest in recent years due to electrical and photonic properties that are far superior to those of other two-dimensional layered semiconductors. The study of long term electrical stability and reliability of black phosphorus field effect transistors (BP-FETs) with technologically relevant thin, and device-selective, gate dielectrics, stressed under realistic (closer to operation) bias and measured using state-of-the-art ultrafast reliability characterization techniques, is essential for their qualification and use in different applications. In this work, air-stable BP-FETs with a thin top-gated dielectric (15 nm Al2O3, SiO2 equivalent thickness of 5 nm) were fabricated and comprehensively characterized for threshold voltage ( Vth) instability under negative gate bias stress at various measurement delays ( tm), stress biases ( VGSTR), temperatures ( T), and stress times ( tstr) for the first time. Thin top-gated oxide enables low VGSTR that is closer to the operating condition and ultrafast Vth measurements with low delay ( tm = 10 μs, due to high drain current) that ensure minimal recovery. The resultant time kinetics of Vth degradation (Δ Vth) shows fast saturation at longer stress times and low-temperature activation energy. Vth instability in these top-gated devices is suggested to be dominated by hole trapping, which is modeled using first-order equations at different VGSTR and T. It is shown that measurements using larger tm show lower degradation magnitude that do not saturate due to recovery artifacts and give inaccurate estimation of hole trap densities. Conventional, thick, and global back-gated oxide BP-FETs were also fabricated and characterized for varying tm (1 ms being the lowest due to a low drain current level for thick oxide), VGSTR, and T to benchmark our top-gated results. Nonsaturating Δ Vth in the back-gated devices is shown to result from recovery artifacts due to the large tm (1 ms and greater) values. Finally, using a VGSTR and T-dependent first-order model, we show that the top-gated Al2O3 BP-FETs with scaled gate oxide thickness can match state-of-the-art Si reliability specifications at operating voltage and room/elevated temperature.

Empirical Drain Current Model of Graphene Field-Effect Transistor for Application as a Circuit Simulation Tool

In this paper, an empirical model of dual gate graphene field-effect transistor (GFET) has been developed. The explicit form of drain current expression has been established analytically based on a drift-diffusion approach. The channel sheet charge density helps us to determine the quantum capacitance more accurately. The channel potential has been derived from the equivalent circuit. The improvement of carrier mobility has been included. The closed form expression is obtained with a few fitting parameters to explore the model characteristics. The model is also valid for single gate technology. The model has been verified against some pioneering experimental results reported in literatures. Model simulation agrees well with existing experimental data. We have also compared the results of the model obtained from NANOHUB online simulator for further verification. The characteristics of small signal parameters of this GFET model have been observed and cut-off frequency has been determined. The developed analytical GFET model is also found to be computationally efficient. It is observed that with ± 10% variation in top gate oxide thickness, maximum drain current and peak transconductance vary by (−11.53%/ + 14%) and (−25%/+31.25%), respectively. The double gate bilayer GFET model is implemented in Verilog-A and verified for a voltage amplifier in SPICE environment.

Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs

This paper reports a two-dimensional (2-D) analytical model for surface potential, electric field, drain current and threshold voltage of a three-dimensional (3-D) Ge/Si heterojunction SOI-Tunnel FinFET (TFinFET) with a SiO2/HfO2 stacked gate oxide structure. The top gate-oxide has been considered thicker than the side gate-oxides to approximate its operation to that of the double-gate (DG) devices. The gate-oxide is assumed to be overlapped on the source region of the device. The 2-D surface potential model of the device is obtained by 2-D Poisson's equation using the superposition technique. The surface potential model has been used for modeling the electric field and drain current of the device. Taylor's series expansion has been adopted to develop the threshold voltage model of the device. The effect of mobile charge also included in the Poisson's equation for improving the accuracy of the proposed model. The model results have been validated by comparing the Synopsys 3-D TCAD simulation data for different parameters such as the gate length, drain voltage, and gate-oxide thickness of the proposed TFinFET device.

Junctionless nanowire transistors parameters extraction based on drain current measurements

The aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction mechanism than inversion-mode transistors, the methods developed for the latter devices either are not compatible or cannot be directly applied to JNTs before a deep analysis on their applicability. The current work analyzes the extraction of the series resistance, including a discussion about the influence of the first and second order mobility degradation factors, flatband voltage and low field mobility in junctionless transistors based only on static drain current curves. An analysis of the method accuracy considering the influence of the channel length, nanowire width and height, gate oxide thickness and doping concentration is also presented for devices with different characteristics through three-dimensional numerical simulations. The inclusion of the second order effects in a drain current model is also shown, considering the extracted values. The method applicability is also successfully demonstrated in experimental devices.

Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening

In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by $SS(T) = \ln10~k_BT/e$. However, recent low-temperature studies of different advanced CMOS technologies have reported $SS$(4K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of $SS(T)$ in 28nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying Fermi-Dirac statistics. This results in a subthreshold $I_{D}\sim e^{eV_{GS}/k_BT_0}$ for $T_0=35$K with saturation value $SS(T<T_0) = \ln 10~k_BT_0/e$. The proposed model adequately describes the experimental data of $SS(T)$ from 300 down to 4K using $k_BT_0 \simeq 3$meV for the width of the exponential tail and can also accurately describe $SS(I_{D})$ within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and design of cryogenic circuits.

Research for radiation-hardened high-voltage SOI LDMOS

Based on the silicon-on-insulator (SOI) technology and radiation-hardened silicon gate (RSG) process, a radiation-hardened high-voltage lateral double-diffused MOSFET (LDMOS) device is presented in this paper. With the gate supply voltage of 30 V, the LDMOS device has a gate oxide thickness of 120 nm, and the RSG process is effective in reducing the total ionizing dose (TID) radiation-induced threshold voltage shift. The p-type ion implantation process and gate-enclosed layout topology are used to prevent radiation-induced leakage current through a parasitic path under the bird's beak and at the deep trench corner, and the device is compatible with high-voltage SOI CMOS process. In the proposed LDMOS, the total ionizing dose radiation degradation for the ON bias is more sensitive than the OFF bias. The experiment results show that the SOI LDMOS has a negative threshold voltage shift of 1.12 V, breakdown voltage of 135 V, and off-state leakage current of 0.92 pA/μm at an accumulated dose level of 100 krad (Si).

Deep insights into electrical parameters due to metal gate WFV for different gate oxide thickness in Si step FinFET

A systematic investigation of the impact of Ti metal gate work function variability (WFV) on various electrical parameters against variation in gate oxide thickness in both step-FinFET and conventional FinFET (C-FinFET) using technology computer-aided design simulation is reported. It is seen that WFV of Ti metal gate has a significant influence on electrical parameters such as threshold voltage ( σV T ), subthreshold swing ( σ SS), on current ( σI on ), and off current ( σI off ) with variation in gate oxide thickness. It is also perceived that the impact of WFV of Ti gate material in step-FinFET is lesser than C-FinFET. Histograms of various electrical parameters are presented for better understanding of the statistical impact of WFV of Ti metal gate in both the structures.

An Analytical Drain Current Model of Gate-On-Source/Channel SOI-TFET

This paper presents an analytical drain current model of Gate-on-Source/Channel SOI-TFET. While deriving the drain current, at first surface potential is derived considering the effect of back gate and considering the effect of bandgap narrowing, energy bands are derived from this surface potential. Finally, the drain current model of Gate-on-Source/Channel SOI-TFET is developed using maximum generation rate of the device. Considering the effect of local minimum present in the energy band diagram of Gate-on-Source/Channel SOI-TFET, maximum generation rate is calculated using a different approach by considering the difference of surface potential between the source region with no gate overlap and the position of local minimum. The proposed model is investigated for front gate voltage, back gate voltage, drain voltage variation. Scalability of the proposed model is analyzed by changing the front gate oxide thickness and body thickness. The model results are compared with the TCAD simulated data to validate the model.

Hall effect mobility in inversion layer of 4H-SiC MOSFETs with a thermally grown gate oxide

The inversion layer mobility of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with a thermally grown gate oxide was investigated using Hall effect measurements. To clarify the fundamental scattering properties of inversion layer mobility in SiO2/4H-SiC systems, we examined the effects of nitridation treatment after thermal oxidation and the gate oxide thickness on Hall effect mobility (μHall) in the inversion layer of 4H-SiC MOSFETs. The effect of nitridation treatment after thermal oxidation on phonon-limited mobility (μphonon) was investigated by using a p-type well region with an epitaxial layer with extremely low acceptor concentration (NA). It was found that nitridation treatment had little effect on μphonon for gate oxide thicknesses of 5 nm and 50 nm. The carrier transport properties were experimentally evaluated from the viewpoint of the effects of gate oxide thickness and nitridation treatment after thermal oxidation. Here, we used samples with a moderate NA of 1 × 1016 cm−3, which enabled us to distinguish μphonon, Coulomb-limited mobility (μCoulomb) and surface roughness-limited mobility (μSR). It was found that thermally grown SiO2/4H-SiC systems have the common feature that the dominant scattering components in the inversion layer are phonon scattering and Coulomb scattering and not surface roughness scattering at room temperature within the measured effective normal field (Eeff).

2-D Modeling of Dual-Gate MOSFET Devices Using Quintic Splines

This paper is the first known composition to demonstrate the application of quintic splines in the development of a dual-gate MOSFET model based on the well-known drift-diffusion system of differential equations used in semiconductor analysis. The techniques and methodologies presented advance the current state of the art in this particular area by implementing improved 2-D numerical techniques and avoiding the use of common accuracy reducing assumptions to decrease semiconductor equation complexity and execution time. This results in a model that is valid in all regions of operation, includes Non-Quasi static transient behavior, accounts for short channel effects, and allows researchers to predict the real world manufacturing effects of gate oxide thickness imperfections and applied gate voltage disparities. Model validation was accomplished by comparing simulation results to previously published experimental data for long and short channel devices as well as data generated using an established commercial product. In addition, a subsequent paper submission is planned to demonstrate the application of this modeling method in determining frequency response for simple CMOS circuits.

Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET

In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation.

Parameterized Comparison of Nanotransistors Based on CNT and GNR Materials: Effect of Variation in Gate Oxide Thickness and Dielectric Constant

Silicon based technology encounters scaling parameters that prohibit the advancement of transistor technology. Graphene nanoribbons (GNR) and carbon nanotubes (CNT) are often considered the predominating devices to replace silicon technology. Carbon nanotube field effect transistors (CNTFETs) are considered the most promising devices because of their most interesting properties such as high current carrying ability (∼ 1010 A/cm2), excellent carrier mobility, scalability, high reliability for elevated temperature operation, and negligible leakage current. In this paper, a comparative analysis of CNTFET and graphene nanoribbon field effect transistors (GNRFET) is presented. The results of simulations are presented, and comparisons of devices are done based on different parameters listed as ION/IOFF current ratio, trans-conductance, and inverse subthreshold slope using NanoTCAD ViDES. After simulation, it is shown that CNTFET offers better results for ION/IOFF on the order of 106, subthreshold swing (SS) as 74.4 mV/dec, and transconductance as 7.6 μS. Further the effect of oxide thickness and dielectric constant has been studied for both FET devices. At the end, it is concluded that CNTFET offers better simulation result than that of GNRFET.

Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, &lt;em&gt;thermal&lt;/em&gt;&lt;em&gt; &lt;/em&gt;emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

Influence of Doping and Splitting of Source in a Group IV Material Based Tunnel Field Effect Transistor

In this work, the effect of abrupt source doping in a tunnel field effect transistor (TFET) using SiGe as the source and drain material is investigated for future low-voltage and high-power applications. The effect of critical device factors, such as dielectric material and gate oxide thickness and dependency on the mole fraction, are examined. The results of the proposed SiGe-Si-SiGe TFET structure are compared with existing data of Si TFET and SiGe-Si-Si TFET with and without abrupt doping. The proposed structure shows better ION/IOFF ratio of the order of 1011 and a sub-threshold swing of 18.18 mV/decade, which ensures fast switching applications of the device.

Self-Organized Ge Nanospherical Gate/SiO2/Si0.15Ge0.85–Nanosheet n-FETs Featuring High ON-OFF Drain Current Ratio

We reported experimental fabrication and characterization of Si0.15Ge0.85 n-MOSFETs comprising a gate-stacking heterostructure of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate in a self-organization approach. This unique gate-stacking heterostructure is simultaneously produced in a single oxidation step as a consequence of an exquisitely controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials at 900 °C. Process-controlled tunability of nanospherical gate of 60–100 nm in diameter, gate oxide thickness of 3 nm, and Si0.15Ge0.85 nanosheet with compressive strain of −2.5% was achieved. Superior gate modulation is evidenced by subthreshold slope of 150 mV/dec and ${I} _{\mathrm{ ON}}/{I} _{\mathrm{ OFF}}>5\times 10^{8}$ ( ${I} _{\mathrm{ OFF}} and ${I} _{\mathrm{ ON}}>500~\mu \text{A}/\mu \text{m}$ ) measured at $V_{G}= +1V$ , $V_{D} = +1$ V, and $T = 80$ K for our device with channel length of 75 nm.

Threshold Voltage Characteristics for Silicon Nanowire Field-Effect Transistor With a Double-Layer Gate Structure

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells.

Optimisation of pocket doped junctionless TFET and its application in digital inverter

In this work, a device called pocket doped junctionless tunnel field-effect transistor (JL-TFET) for digital inverter application is proposed. The operation of this device is subjected to junctionless technique and initially it has an N+–N+–N+ structure. This device utilises a SiGe N+ pocket at the source side and a dual gate namely, fixed gate and control gate. By keeping the fixed gate voltage below its flat band voltage and varying the control gate from 0 to VDD, the device is converted from the N+–N+–N+ structure to P–I–N structure and operates like a tunnel field-effect transistor (TFET). The inclusion of N+ pocket gives an additional tunnelling path perpendicular to the gate-oxide thickness. A brief examination of the proposed device has been done on the impacts of the work-function variations of both the gate metals. A subthreshold swing of 43.6 mV/dec is obtained for fixed and control gate work-function of 5 and 4.5 eV, respectively. The proposed device gives the drain current of 5.7 × 10−4 A approximately twice that of conventional JL-TFET. Further, an radio frequency analysis of the device is done for different parameters such as drain current (ID), total gate capacitance (Cgg), transconductance (gm) and cut-off frequency (fT) and the outcomes are compared with conventional JL-TFET. The device is found to be suitable for high-frequency application. Lastly, it is applied on inverter circuit and its voltage transfer characteristics are studied.

A 28 ppm/°C, 2.54 ppm/V, −77 dB@100 Hz pico-ampere voltage reference for high-end IoT systems

This paper presents a pico-ampere voltage reference for IoT systems with high performance in line regulation and power supply rejection ratio (PSRR). Based on the leakage current characteristics of MOSFETs, the reference voltage is obtained by taking advantage of the threshold voltage differences between two types of MOSFETs with different gate oxide thicknesses. By employing a self-regulation technique, the impacts of drain-induced barrier lowering (DIBL), gate-induced drain leakage (GIDL) and gate-drain capacitance feedthrough effects can be mitigated, resulting in high performance in line regulation and PSRR. Based on a 0.18 μm standard CMOS process, post-layout simulation results show the temperature coefficient is 28.0 ppm/°C over the temperature range of 0–120 °C with a 0.6 V supply voltage. The line regulation is 2.54 ppm/V, which is at least two orders of magnitude lower than existing designs in the literature. The PSRR is −77 dB@100 Hz that is improved by at least 10 dB over existing designs in the literature.

Silicon slot fin waveguide on bonded double-SOI for a low-power accumulation modulator fabricated by an anisotropic wet etching technique.

We propose a new low VπL, fully-crystalline, accumulation modulator design based on a thin horizontal gate oxide slot fin waveguide, on bonded double Silicon-on-Insulator (SOI). A combination of anisotropic wet etching and the mirrored crystal alignment of the top and bottom SOI layers allows us for the first time to selectively pattern the bottom layer from above. Simulations presented herein show a VπL = 0.17Vcm. Fin-waveguides and passive Mach-Zehnder Interferometer (MZI) devices with fin-waveguide phase shifters have been fabricated, with the fin-waveguides having a transmission loss of 5.8dB/mm and a 13.5nm thick internal gate oxide slot.