Abstract
In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation.
Highlights
The downscale of the conventional MOSFETs devices to nanoscale regime has been the driving force of the semiconductor industry [1,2,3]
Double gate structures [10,11,12] introduce the concept of volume inversion leading to higher current, better scalability, and increased conductance than conventional MOSFETs, but its use is limited based on the cost of production and process complexity
In terms of current drive the cylindrical surrounding-gate (CSG) MOSFETs have lesser current compared with the DG MOSFET, its extensive use is limited for high performance application [22]
Summary
The downscale of the conventional MOSFETs devices to nanoscale regime has been the driving force of the semiconductor industry [1,2,3]. The most enhancing feature of the CSG MOSFET when compared to other novel structures, like single gate, pi gate, and double gate, is its geometric structure This device structure increases the packing density, and most importantly leads to better controllability of the gate over the channel [17,21]. There is need to improve on the geometric structure of the CSG MOSFET to enhance the current drive, the gate control over the channel and further improve the SCEs immunity at the nanoscale regime. The minimum surface potential is further extended in the derivation of the threshold voltage model, subthreshold current, and subthreshold swing of the device structure.
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