Optimisation of pocket doped junctionless TFET and its application in digital inverter

Abstract

In this work, a device called pocket doped junctionless tunnel field-effect transistor (JL-TFET) for digital inverter application is proposed. The operation of this device is subjected to junctionless technique and initially it has an N+–N+–N+ structure. This device utilises a SiGe N+ pocket at the source side and a dual gate namely, fixed gate and control gate. By keeping the fixed gate voltage below its flat band voltage and varying the control gate from 0 to VDD, the device is converted from the N+–N+–N+ structure to P–I–N structure and operates like a tunnel field-effect transistor (TFET). The inclusion of N+ pocket gives an additional tunnelling path perpendicular to the gate-oxide thickness. A brief examination of the proposed device has been done on the impacts of the work-function variations of both the gate metals. A subthreshold swing of 43.6 mV/dec is obtained for fixed and control gate work-function of 5 and 4.5 eV, respectively. The proposed device gives the drain current of 5.7 × 10−4 A approximately twice that of conventional JL-TFET. Further, an radio frequency analysis of the device is done for different parameters such as drain current (ID), total gate capacitance (Cgg), transconductance (gm) and cut-off frequency (fT) and the outcomes are compared with conventional JL-TFET. The device is found to be suitable for high-frequency application. Lastly, it is applied on inverter circuit and its voltage transfer characteristics are studied.