An Analytical Drain Current Model of Gate-On-Source/Channel SOI-TFET

Abstract

This paper presents an analytical drain current model of Gate-on-Source/Channel SOI-TFET. While deriving the drain current, at first surface potential is derived considering the effect of back gate and considering the effect of bandgap narrowing, energy bands are derived from this surface potential. Finally, the drain current model of Gate-on-Source/Channel SOI-TFET is developed using maximum generation rate of the device. Considering the effect of local minimum present in the energy band diagram of Gate-on-Source/Channel SOI-TFET, maximum generation rate is calculated using a different approach by considering the difference of surface potential between the source region with no gate overlap and the position of local minimum. The proposed model is investigated for front gate voltage, back gate voltage, drain voltage variation. Scalability of the proposed model is analyzed by changing the front gate oxide thickness and body thickness. The model results are compared with the TCAD simulated data to validate the model.