Back-gate bias effect on partially depleted SOI/MOS back-gate performances under radiation condition

Abstract

According to the partially depleted SOI/MOS device's band gap, starting with the electric field, which is a factor of back-gate charge stack, we combine SOI device capacitance model and flat capacitance model for finding the way to keep electric field at the interface of Si/SiO2, and build a back-gate bias model. For validating the new model, we use alloy-agglomeration at the back gate. After radiation experiments, we compare the results of back-gate effect on NMOS with those on PMOS. It is concluded that as far as NMOS is concerned, negative voltage at back-gate can eliminate the back-gate effect which influence the performance of device, and improves the performance of front-gate. However negative voltage at back-gate makes the performance of PMOS worse. Therefore, when we use the back-gate bias to improve the performance of device, we must consider the performances of NMOS and PMOS and compromise the choice of the voltage which is applied to the back-gate. This research supplies not only a design scheme for hardening back-gate effect of SOI devices under radiation condition, but also a support in theory for integrated circuit design and manufacture, which is used in space.