Investigation of Back Gate Effects on the Electrical Characteristics of Fully-Depleted Silicon-On-Insulator MOSFET

Abstract

Dual-Gate operation of Fully-Depleted Silicon-on-Insulator (FDSOI) MOSFET has significant effects on its electrical characteristics. This paper illustrates a comparative analysis of back gate effects on an FDSOI MOSFET for different channel lengths, with varying SOI active layer thickness and buried oxide (BOX) layer thickness. Performance analysis has been done through simulations performed on SentaurusTM Technology Computer Aided Design (TCAD) tool to study the back gate effect on threshold voltage of the transistor, transconductance curve and electrostatic potential across the transistor channel. It was found that thicker active layer significantly reduces the effect of applying back gate bias while reducing the buried oxide thickness enhances the front gate threshold voltage dependence on back gate bias. Transconductance curves show secondary peak in long channel devices on applying positive back gate bias, with gain broadening whereas for short channel devices, the gain peak shift is more pronounced with applied back gate bias.