Synopsys TCAD Research Articles

Design and investigation of gaussian doped junction free SMDG and TMDG-TFET for analog/RF applications

This research investigates four variants of Gaussian Doped (GD) Double Gate Single Material and Tri-Material Junction-Free Tunnel-Field-Effect-Transistors (GD-DG-JF-TFETs) to optimize their performance in analog and RF applications. The analysis is conducted using the Sentaurus Synopsis TCAD simulation tool, reveals a Subthreshold Swing (SS) as low as 38 mV/dec, exceptionally higher cut-off-frequency (f t ) and maximum-oscillation-frequency ( fmax ) of 516 GHz and 895 GHz, respectively. The proposed TMDG-JF-TFET enhances band-to-band tunneling between the drain and source regions, resulting in an extremely low-off-state-current (I off) of 9.6 fA and large-on-state current (I ON) of 6.7 mA in Permittivity of high-k (HfO 2 = 25) and low-k (SiO 2 = 3.8) based structures.Compared to conventional SMDG technologies, the TMDG structures exhibits 36% reduction in SS, a 16% improvement in f t , an 18% enhancement in fmax and 17% increase in I ON. These improvements demonstrate that TMDG-based TFETs are superior devices for ultra-low-power-integrated-circuit-applications.

Experiment and Simulation Analysis of MSM Photodetector Based on Cubic Boron Nitride Single Crystals

The cubic boron nitride (cBN) single crystals present a higher expectation for deep ultraviolet (DUV) detectors. Simulations have been carried out using Synopsys TCAD to improve the performance of detectors. The light and dark current were observed by changing the parameters such as electrode spacing, doping concentration. The detector has the maximum response with the doping concentration of 1013 cm−3. The light-to-dark current is up to about 60 with an electrode width and spacing of 15 µm. The photocurrent was measured based on the prototype device.

Design and performance analysis of tri-layered strained Si/Si1–x Ge x /Si heterostructure DG feedback FET

This work presents the design and performance analysis of a tri-layered strained Si/Si1−x Ge x /Si heterostructure double gate feedback field-effect transistor (DG FBFET). The proposed DG FBFET is designed by introducing biaxial strain in the device by sandwiching a Si1−x Ge x layer between two thin Si layers to provide high ON current as well as ultra-steep switching characteristics. The device offers a significantly high ON current (3.4 x 10−3 A/μm), high I ON /I OFF ratio (∼1010), a large memory window of 1.06 V, and an extremely low subthreshold swing (∼0.3 μ V/decade), which can be very useful for memory and neuromorphic applications. Furthermore, the ON/OFF switching of the device has been accomplished at a lower threshold voltage (0.287 V), allowing it to be utilized in low-power electronics. Synopsys TCAD tool has been used to create the device structure and analyze the electrical performances of the device.

Simulation study of multi-source hetero-junction TFET-based capacitor less 1T DRAM for low power applications

A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The analysis of the three memory functions: Write, Hold and Read of 1T DRAM has been carried out using Synopsys TCAD simulations. A storage region of Ge material is used for the accumulation of holes/to store the charge carriers. The variation in length of Ge-storage region, under lap length (Lunder), and temperature is performed to analyse the DRAM performance. In the Write operation, the tunneling window reduces to 15 nm and holes can be easily stored in the Ge-storage region. In case of Hold1 and Read1 operations, the potential barriers are reduced by 0.24 eV, and 0.1 eV respectively. In the proposed multi-source TFET with 14 nm gate length, read current ratio i.e. IR1/IR0 of 4.4, retention time (RT) greater than 10 sec, and sense margin (SM) of 1.27 × 10−6 A/µm is achieved at room temperature. The proposed multi-source TFET based 1T DRAM is operating at very low gate voltages. Therefore, this device is well suited for low power applications.

Two-dimensional hydrodynamic modelling of AlGaN/GaN transistor-based THz detectors

Here, we report on numerical modelling of AlGaN/GaN HEMT terahertz detectors using a two-dimensional solver based on three Boltzmann transport equation (BTE) moments and the Poisson equation. We use the Synopsys TCAD Sentaurus program package, which offers a wide material database and the possibility to include traps and polarization charges for the formation of the channel without any doping. The implications of different levels of model simplifications are addressed both analytically and numerically. We calculated the current responsivity ℜI, to THz radiation on the drain voltage in the frequency range 0.01-3.0 THz for three AlGaN layer thicknesses d = 15, 20 and 25 nm and different gate lengths. We demonstrate that only a hydrodynamic model can reproduce the change in the sign in current responsivity at the gate voltage UG0 (ℜI = 0 at UG = UG0). The energy flux factor in the energy balance equation determines this effect. For the simulated structures, we find that the noise equivalent power may be as low as 0.1 pW/√Hz at 0.04 THz and 10 pW/√Hz at 3.0 THz.

TCAD Simulation of X-ray irradiated Si microstrip detector : Impact on full depletion voltage and leakage current

In the intense x-ray radiation environment at synchrotron sources, it is reported that the performance of the silicon pixel detectors degrades with an increasing x-ray dose up to 10 MGy. To study the impact of x-ray irradiation effects in the n-Fz Si microstrip detector, the microscopic radiation damage parameters of x-ray radiation were extracted from the current–voltage, and capacitance-voltage experiments on test Si microstrip detector. The damage parameters are implemented in Synopsys TCAD. In this paper, we have irradiated the test structure up to 10 MGy, and the results on full depletion voltage, and leakage current are compared with the TCAD simulation results. A very good agreement in between experimental and simulation results is observed in the leakage current for the non-irradiated, and 1 MGy irradiated detectors, where for high doses up to 10 MGy, experimental leakage current was fifty times higher than the simulated leakage current at full depletion voltage. The full depletion voltage in 0 MGy detector is also well matched with the simulation result, and further, it shows the full depletion voltage performance of x-ray irradiated detector. Finally, the new detector design specifications and process parameters are proposed for the optimum performance of the radiation hard p+n Si pixel detector equipped with guard rigs at cut edge for the next generation photon science applications.

Electro-thermo-mechanical modelling of a SiC MOSFET transistor under non-destructive short-circuit

This article presents an electro-thermo-mechanical simulation of a SiC MOSFET transistor. The simulation was performed using Synopsis TCAD for electric modelling and ANSYS for thermo-mechanical modelling. A method upgrading stress estimation of a SiC MOSFET chip is suggested. It includes a bridge between Sentaurus TCAD and ANSYS mechanical, an aluminium's fusion model and a multiscale simulation. Finally, a difference between an isolated cell and a cell within a chip has been noticed. The results of the simulation provide valuable insights into the behaviour of SiC MOSFET transistors during short-circuit events.

Linearity and RF analysis of double gate reverse T-shaped TFET with L-shaped pocket across the Si-Ge source region

In this work, a comprehensive investigation of the twin gate or double gate reverse T-shaped channel TFET (RT-DG-TFET) along with the heavily doped pocket at the source-channel interface is portrayed. Here the pockets have been placed in various places on the device like vertical and horizontal pockets across the source and the channel region, a pocket at the center of the source, a pocket near to tunneling junction, and an L-shaped pocket across the source-channel interface. All these structures are investigated and the pocket is doped with P-type impurities. Linearity and RF analysis are investigated using the Synopsis TCAD Sentaurus tools and compared among all these structures. The L-shaped pocket shows better results compared to others.

Performance Analysis of SOI-Tunnel FET with AlxGa1-xAs Channel Material

Background: Tunnel Field-effect transistor (TFETs) has appeared as a promising candidate due to its steep slope (SS<60 mV/dec), which can be used for low-power applications Objectives: Authors investigated AlxGa1-xAs as the channel material in Silicon-on-Insulator (SOI) TFETs and compared it to other existing channel materials, SiGe, Ge, Si, Ge, Strained Si, and GaAs. Methods: For the entire device study, the mole fraction x = 0.2 has been used in AlxGa1-xAs channel material. The direct energy bandgap for Al0.2Ga0.8As has been used because the mole fraction is less than 0.4. The Al0.2Ga0.8As-based device has been analyzed in terms of Direct Current (DC) and Alternating Current (AC) characteristics using the Synopsys TCAD tool. Results: The proposed device offers enhanced switching speed with a high on/off ratio of ~1012 and a steep subthreshold swing of 30 mv/dec As a channel material, Al0.2Ga0.8As also enhances the miller capacitance of the device, which is one of the essential requirements of the device performance. Conclusion: In next-generation devices, Al0.2Ga0.8As as channel material and TFET device based on this channel material act as a promising contender for low-power applications.

(Invited) A Novel Computational Framework for Simulations of Bio-Field Effect Transistors

In this paper, we present the simulation results of a BioFET using a novel simulation methodology implemented in a computational framework called the Biomolecule-Oxide Simulator (BOxSim). Our novel simulation methodology is based on Gouy-Chapman-Stern and the modified Site-binding models [1][2]. Moreover, our “BOxSim” framework is the computational simulation framework that works on the hierarchical inclusion of interdependent functions to operate multiple models simultaneously. BOxSim is flexible simulation environment which considers the problems of reactive sites from oxide surfaces or non-specific bindings along with the noise present in the experimental signal to calibrate and extract the required device output characteristics [3]. It can help in generating the sensor response which can be experimentally calibrated to confirm the surface density of the specific and non-specific binding as a yield of the process while filtering the noise with the help of the developed methodology. BOxSim is designed in a way [shown in the attached block diagram] that can interact with the commercial tool (e.g., Synopsys TCAD) and our inhouse-simulator called Nano-electronic Simulation Software (NESS) to simulate the main device characteristics for designing either Ion-sensitive FET (ISFET) or Chem/Bio-FET based on the application. Industry-standard compact (BSIM) models can also be used to interact with the BOxSim which takes the generated surface potential from the BOxSim simulator and transfers it into a circuit simulator to evaluate various ISFET circuit designs.To show the capabilities of our BOxSim framework, as input we have considered several oxides, amino acids (AA) and short peptides which generate distinct signatures for arch AA or peptide. We have investigated the impact of various high-k dielectric materials [4][5] as the gate oxide on important Figures of Merit (FoM) such as current in the channel of the device, surface potential (Ψ o ), sensitivity and intrinsic buffer capacitance [6]. More importantly, the variation of differential capacitance (CT ) with the second gradient of drain current (d2 I o /dpH2 ) and surface potential (d2 Ψ o /dpH2 ) are used to uniquely identify the signatures of different amino acids or peptides. Fig. 1 shows the characteristics of different oxides with respect to the pH variation. The surface potential of oxides is dependent on the affinity constants and the zero-crossover point represents the zwitterion state. Similarly, we have simulated the detection process of different AA such as Glutamic Acid (E) and Lysine (K) immobilized with carboxyl (C-Imm.) or amine (N-Imm.) terminal [Fig. 2]. The affinity constants, isoelectric point, and density of amino acids can be extracted from the d2Ψo/dpH2 variation with the bulk pH. Other than amino acids, we have shown the distinct features of short a peptide Phenylalanine-Proline (FP) immobilized with carboxyl-terminal and the addition of Glutamic Acid to the sequence [Fig. 3]. The sensor output can be observed as the variation of drain current with the pH for the immobilized peptide sequence on the sensing surface. We have also confirmed the reliability of the designed model by calibrating the simulated results with the experimental data [7] for different physical conditions [Fig. 4]. The proposed method can be helpful in defining an efficient method for label-free protein sequencing.

GaSb/GaAs Type‐II heterojunction GAA‐TFET with core source for enhanced analog/RF performance and reliability

AbstractFor the first time, a novel source extension heterojunction gate‐all‐around tunnel FET (SE‐GAA‐TFET) is proposed and examined using Synopsys TCAD simulator in this manuscript. SE‐GAA‐TFET is found to exhibit improved performance in terms of various analog/RF and DC parameters. As channel/source (C/S) interface and electric field exerted by gate are perpendicular to each other, radius of channel is downscaled to enhance electric filed, without reducing area of the tunneling. Furthermore, the presence of GaSb/GaAs heterojunction at C/S interface leads to reduction in the effective band overlap, which helps a great number of mobile charges to tunnel through C/S boundary at ON‐state. The consequences of variation in different geometrical metrics are evaluated to optimize the device performance. SE‐GAA‐TFET is found to offer a current switching ratio (CSR) of ~1013 along with 32.2 mV dec−1 of average sub‐threshold swing (SSAVG). Furthermore, improvement in transconductance and parasitic capacitance boost the cut‐off frequency of SE‐GAA‐TFET up to 37 GHz. Next, both positive and negative traps are introduced at S/C interface and the study reveals that there is no much deviation in parameters of the transfer characteristics like ION, SSAVG, and IOFF of SE‐GAA‐TFET. Next, proper benchmarking is done to compare the performance of the SE‐GAA‐TFET with similar devices available in literature and it is found that proposed SE‐GAA‐TFET exhibits better DC performance due to improved electrostatic behavior. Finally, SE‐GAA‐TFET is found to offer better fall time along with full‐voltage swing when deployed in a resistive load inverter.

Study of Self Heating Effect in the wake of complete and partial bottom dielectric insertion under 5 nm Stacked Nanosheet Transistor

Beyond 7 nm technology nodes, a Stacked Nanosheet Field Effect Transistor (SNT) is a potential candidate to continue device scaling due to its higher ON/OFF current ratio and less Short Channel Effect than FinFET. However, its gate all-around structure with low thermal conductive HiK oxide material exacerbates the Self-Heating Effect (SHE) issue in the SNT. Further, a dielectric inserted beneath SNT to reduce leakage current disrupts the primary heat flow path through the substrate, aggravating the Self Heating Effect (SHE). This study focuses on exploring the thermal aspect of the SNT with partial and complete dielectric insertion under the device from a performance and reliability perspective. A 3D electrothermal analysis has been performed using Synopsys TCAD tool. The effect of partial and complete dielectric insertion under the device on lattice temperature was investigated in the case of single and double-stack nanosheet transistors. The effects of dielectric insertion on channel and substrate temperature were analyzed. Its variation with width, extension length, interface thermal resistance, and the number of sheets and stack pitch of SNT are discussed. Sheet-dependent heat flow through the substrate and source/drain contact explained for different types of SNT structures and its effect on device performance and reliability discussed. To discuss the effect of multiple parameters variation on the lattice temperature of the device, Analysis of Variance (ANOVA) method was used. It was found that complete dielectric insertion leads to a severe heating issue in the SNT compared to partial and without dielectric insertion.

Performance Investigation of a Vertical TFET with Inverted-T Channel for Improved DC and Analog/Radio-Frequency Parameters

In this manuscript, a novel line tunneling based gate-on-source-only TFET with inverted T-shaped channel (ITGOSO-VTFET) is proposed and investigated using Synopsis TCAD 2-D simulator. The GOSO configuration along with dual counter-doped pockets (CDP) improve the ON-state current by enhancing the tunneling rate of charge carriers at source/channel interface while inverted T-shaped channel helps the proposed device in reducing the OFF-state (IOFF) and ambipolar (IAMB) currents. In comparison with double-gate (DG) and GoSo-CDP TFET, the order of IOFF (IAMB) in ITGOSO-VTFET are found to be improved by ∼6 (∼4) and ∼7(∼3), respectively. Furthermore, the impact of varying design parameters is analyzed in order to obtain the optimized performance of the proposed device. Apart from improvement in DC performance, ITGOSO-VTFET is also found to offering a much better analog/RF performance in terms of various parameters like gm, fT, TFP, GBP, and τ, which eventually makes the proposed device more suitable for low power and high-speed applications.

TCAD simulation of the mixed irradiated n-MCz Si detector: Impact on space charges, electric field distribution

In the mixed irradiations at HL-LHC, n- MCz Si as a detector material is reported as a prime applicant. To study the non-homogeneous distribution of space charges and electric field distribution in mixed irradiated p+n MCz silicon pad detectors, four-level numerical modeling of mixed irradiation induced deep traps using microscopic parameters obtained from experimental measurements were implemented in Synopsys T-CAD. These advanced damage model parameters were sufficiently tuned to reproduce the experimental data’s on the full depletion voltage and leakage current at 293K. In this paper, the influence of effective introduction rate of shallower donor deep trap E30 K has been determined using SRH theory calculations for experimental effective doping concentration f and the behavior of space charges and electric field distribution in the presence of deep traps are thoroughly investigated.

Analysis of Bulk and Surface Radiation Damage in n+ in p SFz Si Micro Strip Detectors for the Future High Luminosity Collider Experiments: TCAD Simulation and Measurements

Within the framework of CERN RD50 collaboration, several radiation damage models for n/p-SFz, n-MCz Si have been explored for the better understanding of the experimental results in radiation damage analysis of the irradiated Si detectors. In the present paper, the important review on the microscopic radiation damage model for the p-type SFz Si detector combining the surface and radiation damage effects that can be used to simulate radiation damages effects in the heavily irradiated detectors for the good comparison of the experimental data and simulation result. The surface radiation damage models were extracted from the experimental measurements on the p-MOS capacitor and Gate-Controlled Diodes irradiated by Gamma or X-ray radiations in the range of 10 to 500 Mrad (Si). Whereas, the bulk damage model microscopic parameter was extracted from the experimental (TSC, DLTS) measurements on the n in p-SFz Si microstrip detector. The radiation damage (surface and bulk) models can be fed into the commercial Synopsys TCAD device simulator program for the designing and optimization of the detector, which can be used in the very harsh radiation environment of the HL-LHC, or FCC experiment. The objective of this analysis was to verify the experimental results using the new microscopic radiation damage models on the p-SFz Si for the radiation damage analysis of p- SFz Si detectors irradiated by proton, neutron or mixed at very high fluences. The results were verified by comparison of the experimental data with TCAD simulation.

Simulation Analysis of Noise Components in NCTFET with Ferroelectric Layer in Gate Stack

Tunnel FETs (TFETs) are a strong contender for replacing conventional MOSFETs in lower power applications due to their low off-state current and sub-threshold swing being much lower than 60 mV/decade. The major trade-off is the shortcomings of TFET, which are ambipolar behaviour, low on-state current and large miller capacitance. The various novel structures of TFETs have been proposed by researchers. This work presents one such structure of heterojunction negative capacitance TFET with raised source and gate material overlapping. With the intervention of the ferroelectric layer in the gate stack of TFET, the overall performance of the device has been improved. Further AC DC analysis and electrical noise analysis are carried out for the proposed device to see the impact of improvisations being done in the structure on the input–output characteristics of the device. Synopsys TCAD tool is used to carry out the simulations at low and high frequencies. As per the results obtained, the raised source device using Ge as source material exhibits a high ION of 4.295 × 10−5 A/μm, low IOFF of 6.01 × 10−15 A/μm and sub-threshold slope of 53.75 mV/decade. The proposed device structure is having least ambipolarity and can be used in ultra-low power circuits.

Noise characterisation of GaN current aperture vertical electron transistor metal‐insulated semiconductor field effect transistor with Δ‐shaped gate for low noise radio frequency amplifiers

In this article, vertical CAVET with boron-doped GaN layer as current blocking layer (CBL) for AlGaN/GaN is proposed in this study, and different electrical characteristics of the devices, such as DC (Ids − Vds), small-signal radio frequency and high-frequency microwave noise performances, are characterised using Synopsys TCAD simulations. The vertical CAVET AlGaN/GaN metal-insulated semiconductor field effect transistor (MIS-HEMT) has been found to have a high threshold VT = 6.36 V, drain saturation current, Ids,sat = 3.41 kA/cm2, reduced OFF-state current <10−12 and improved high frequency and noise performances. The findings provide insight on noise sources and provide information on how to improve GaN transistor noise performance. Its useful characterisation tool for learning more about the imperfections in advanced AlGaN/GaN MIS-HEMTs and how they evolve. A two-port noise equivalent-circuit description is used to calculate data for noise. Using data from noise and scattering parameters that have been measured, we evaluated the effect of noise sources due to gate and drain, as well as their correlation. The devices exhibit a minimum noise figure (NFmin) and an equivalent noise resistance (Rn) of 1.21 dB and 20 Ω at 20 GHz, with Vgs = 5 V and Vds = 10 V, which is small and appropriate for low-noise amplifiers with a wide bandwidth. The maximum output power density Pout of 23 dBm and the maximum PAE of 63.3% are achieved for GaN V-shaped CAVET MIS-HEMTs with Vds = 10 V at 3.12 GHz is achieved. A comparison is made between the noise performance of conventional HEMTs, MIS-HEMTs and FETs. The methods for obtaining the noise figure (NFmin) and other noise metrics are then explained and compared with those found in the literature.

Comparative Study of L-shaped and U-shaped TFET Device with Temperature Variations

Background: In the nanometer regime, the impact of temperature is quite dominant in the device characteristics. Objectives: A comparative study of L-shaped Tunnel Field Effect Transistors (TFETs) and Ushaped TFETs with temperature variation. Methods: The effect of temperature has been studied for the device characteristics in terms of surface potential, electric field, and transfer characteristics using the Synopsys TCAD tool. Results: The ON current and OFF current of L-shaped and U-shaped TFETs structure shows the enhanced performance due to the large area of channel length. The addition of n-type pocket under the source enhances both devices ON current and OFF current. Both L-shaped and U-shaped TFETs structures are easy to fabricate and cost-effective due to the use of already established Si technology. Conclusion: In next-generation devices, the superior performance of L and U-shaped TFETs structure makes it a promising contender for low power applications as their subthreshold swing (SS) is less than 60 mV/decade is observed.

Performance enhancement of normally off InAlN/AlN/GaN HEMT using aluminium gallium nitride back barrier

In the present work, we have studied the influence of Aluminium Gallium Nitride (AlGaN) back-barrier (BB) thickness on the direct current (DC) and short channel effects (SCEs) of lattice matched In0.17Al0.83N/AlN/GaN Gate-Recessed normally off high electron mobility transistor (HEMT) grown on silicon carbide substrate. The extensive simulations are done by the 2Dimenssional synopsis TCAD by means of Hydrodynamic (HD) mobility model and calibrated with the experimental result. The DC performance of the device has been studied using the simulations for different BB thickness (tbb) and a comparison was made with regard to the device without BB for gate length (Lg) 50 nm and 75 nm. The result indicates that use of AlGaN BB has several advantages like improving the SCEs, reducing leakage current and resulting higher threshold voltage (Vth). Therefore the implementation of AlGaN BB in related devices perhaps another way out for high power and digital switching purpose.

An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by [Formula: see text]80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160[Formula: see text][Formula: see text]/mg in 32-nm CMOS technology.