Study of Self Heating Effect in the wake of complete and partial bottom dielectric insertion under 5 nm Stacked Nanosheet Transistor

Abstract

Beyond 7 nm technology nodes, a Stacked Nanosheet Field Effect Transistor (SNT) is a potential candidate to continue device scaling due to its higher ON/OFF current ratio and less Short Channel Effect than FinFET. However, its gate all-around structure with low thermal conductive HiK oxide material exacerbates the Self-Heating Effect (SHE) issue in the SNT. Further, a dielectric inserted beneath SNT to reduce leakage current disrupts the primary heat flow path through the substrate, aggravating the Self Heating Effect (SHE). This study focuses on exploring the thermal aspect of the SNT with partial and complete dielectric insertion under the device from a performance and reliability perspective. A 3D electrothermal analysis has been performed using Synopsys TCAD tool. The effect of partial and complete dielectric insertion under the device on lattice temperature was investigated in the case of single and double-stack nanosheet transistors. The effects of dielectric insertion on channel and substrate temperature were analyzed. Its variation with width, extension length, interface thermal resistance, and the number of sheets and stack pitch of SNT are discussed. Sheet-dependent heat flow through the substrate and source/drain contact explained for different types of SNT structures and its effect on device performance and reliability discussed. To discuss the effect of multiple parameters variation on the lattice temperature of the device, Analysis of Variance (ANOVA) method was used. It was found that complete dielectric insertion leads to a severe heating issue in the SNT compared to partial and without dielectric insertion.