Simulation Analysis of Noise Components in NCTFET with Ferroelectric Layer in Gate Stack

Abstract

Tunnel FETs (TFETs) are a strong contender for replacing conventional MOSFETs in lower power applications due to their low off-state current and sub-threshold swing being much lower than 60 mV/decade. The major trade-off is the shortcomings of TFET, which are ambipolar behaviour, low on-state current and large miller capacitance. The various novel structures of TFETs have been proposed by researchers. This work presents one such structure of heterojunction negative capacitance TFET with raised source and gate material overlapping. With the intervention of the ferroelectric layer in the gate stack of TFET, the overall performance of the device has been improved. Further AC DC analysis and electrical noise analysis are carried out for the proposed device to see the impact of improvisations being done in the structure on the input–output characteristics of the device. Synopsys TCAD tool is used to carry out the simulations at low and high frequencies. As per the results obtained, the raised source device using Ge as source material exhibits a high ION of 4.295 × 10−5 A/μm, low IOFF of 6.01 × 10−15 A/μm and sub-threshold slope of 53.75 mV/decade. The proposed device structure is having least ambipolarity and can be used in ultra-low power circuits.