Synopsys TCAD Research Articles

Micro-features of ambipolar snapback behaviour under high current injection to design capacitorless memory device

This paper presents micro-features of capacitorless memory cells based on snapback phenomenon and modeling of space-charges. 2—Dimensional gate grounded NMOS structure is specified and its operational window of the memory cell is inspected using the Synopsys TCAD tool. This work examines snapback behaviour in one transistor DRAM memory cell in the absence of a storage capacitor under zero gate bias and applied ramp of high current at the drain terminal. Carrier electrostatics and memory cell mechanisms are also explored by adjusting the slope of the high current ramp. The process variation is examined for different parameters in the device. The current crowding phenomenon due to the injection of electrons and holes is investigated, giving rise to ambipolar behaviour. Due to the snapback, redistribution of electron and hole current is investigated. This work also evaluates the impact on electrostatic potential along channel and bulk under the snapback. It explains the dependency of snapback on potential build-up. Post-snapback electron current flipping presents the flow line near the gate region. The bipolar activity is manifested in surface and bulk regions to show its impact through analytics. The effect of gate biasing is also examined under the applied current ramp.

Sensitivity optimization of a Double-Gated ISFET pH-sensor with HfO2/SiO2 gate dielectric stack

This paper investigates the sensitivity enhancement of Ion-Sensitive Field Effect Transistor (ISFET) pH-sensor using double-gate operation and illustrates how different structure modifications between the top and back oxides give different sensitivity gain factors. The gain factor is controlled through top and back oxide thickness, channel thickness and SiGe channel material. The sensitivity at the back gate is 59.52 mV/pH (27 °C) and the amplified sensitivity at the front gate reaches 476.54 ±33 mV/pH (27 °C). Furthermore, the issues related to high sensitivity-amplification such as sensitivity variation and dielectric breakdown are discussed, followed by optimization of the device structure in the linear regime to overcome them. Stacking a thin HfO2 layer over the top SiO2 layer helps in preventing dielectric breakdown at high sensitivity analysis. Synopsys TCAD is utilized for this proposed work with the electrolyte material and site-binding reactions being modeled through user-defined features of TCAD with explicit references from experimental data.

TCAD Modeling of Resistive-Switching of HfO2 Memristors: Efficient Device-Circuit Co-Design for Neuromorphic Systems

In neuromorphic computing, memristors (or “memory resistors”) have been primarily studied as key elements in artificial synapse implementations, where the memristor provides a variable weight with intrinsic long-term memory capabilities, based on its modifiable resistive-switching characteristics. Here, we demonstrate an efficient methodology for simulating resistive-switching of HfO2 memristors within Synopsys TCAD Sentaurus—a well established, versatile framework for electronic device simulation, visualization and modeling. Kinetic Monte Carlo is used to model the temporal dynamics of filament formation and rupture wherein additional band-to-trap electronic transitions are included to account for polaronic effects due to strong electron-lattice coupling in HfO2. The conductive filament is modeled as oxygen vacancies which behave as electron traps as opposed to ionized donors, consistent with recent experimental data showing p-type conductivity in HfOx films having high oxygen vacancy concentrations and ab-initio calculations showing the increased thermodynamic stability of neutral and charged oxygen vacancies under conditions of electron injection. Pulsed IV characteristics are obtained by inputting the dynamic state of the system—which consists of oxygen ions, unoccupied oxygen vacancies, and occupied oxygen vacancies at various positions—into Synopsis TCAD Sentaurus for quasi-static simulations. This allows direct visualization of filament electrostatics as well as the implementation of a nonlocal, trap-assisted-tunneling model to estimate current-voltage characteristics during switching. The model utilizes effective masses and work functions of the top and bottom electrodes as additional parameters influencing filament dynamics. Together, this approach can be used to provide valuable device- and circuit-level insight, such as forming voltage, resistance levels and success rates of programming operations, as we demonstrate.

CMOS-MEMS Accelerometer With Stepped Suspended Gate FET Array: Design & Analysis

This article presents a novel stepped suspended gate field-effect transistor (SSGFET) array-based <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${z}$ </tex-math></inline-formula> -axis accelerometer with an enhanced detection range. The stepped gate electrode structure of SGFET aids in extending the stable driving range beyond 33.33% of the initial air gap. The stable driving range is extended to 50% of the initial air gap with ~90% increase in the pull-in voltage. Mechanical, electrical, and electromechanical analytical models are developed. These models are validated through microelectromechanical systems (MEMS) simulations using CoventorMP and transistor simulations in Synopsys TCAD. An SSGFET-based common source (CS) amplifier with diode-connected p-MOSFET load is designed and simulated in Cadence Virtuoso using the lookup table (LUT) approach. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$z$ </tex-math></inline-formula> -axis accelerometer exhibits a sensitivity of 38 (mV/g) with a supply voltage of 3.3 V for a dynamic range (DR) of ±6 g with the nonlinearity of about 5.3% comparedtoSGFETswith a planar gate electrode,whichcan detect up to ±4 g with the same sensitivity. The 3-dB bandwidth of the accelerometer is 412 Hz with a noise-limited resolution of 109.31 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> g/(Hz) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/2</sup> . This article also presents a detailed analysis of the relation between the number of gate fragments, the pull-in voltage, stable driving range, and the DR along with a feasible fabrication integration plan.

Linearity performance and intermodulation distortion analysis of D-MOS vertical TFET

Recent trend researches provide potential results of tunnel field effect transistors (TFETs) for being used in many electronic circuit applications. This work studies the comparative analyses of n+ pocket vertical TFET and dual MOSCAP (D-MOS) vertical TFET to determine their compatibility in RF applications. Synopsys TCAD simulation result shows a better ION/IOFF ratio (8.43 × 108), steeper sub-threshold swing (18.67 mV/dec) and an enhanced ambipolarity behavior of the proposed D-MOS VTFET. A comprehensive investigation of both the devices under consideration is performed and comparison has been made on their linearity and intermodulation distortion performances. Certain figure of merits of RF performance such as their higher order transconductance characteristics, second- and third-order voltage intercept points (VIP2 and VIP3), third-order input intercept point (IIP3), third-order intermodulation distortion (IMD3), 1 dB compression point and total harmonic distortions have been explored in this work. From the analyses performed, the proposed dual MOSCAP VTFET is found to be comparatively linear where minimum intermodulation distortions and lesser higher order harmonics are guaranteed. Finally, the status of the proposed TFET is highlighted as an efficient device for RF circuit applications.

A Numerical Investigation of Stacked Oxide Junctionless High K with Vaccum Metal Oxide Semiconductor Field Effect Transistor

The amalgamation of high dielectric permittivity material along with vaccum based dual material junctionless transistor with surrounding gate (DUM-HIK-VAC-JLSG-MOSFET) was investigated in this paper. The diverse oxide gate stack architecture of DUM-HIK-VAC-JLSG-MOSFET abate various effects arise due to channel shrinking. The evaluation of various parameters such as potential distribution in the channel region, electric field (transverse, lateral), transconductance, electron current density and drain current has been analyzed and a comparative statement between DUM-HIK-VAC-JLSG-MOSFET and the single material gate junctionless high k and vaccum double gate MOSFET(SIM-HIK-VAC-JLSG-MOSFET). The commingle of high dielectric permittivity material with vaccum as gate oxide stack and junctionless transistor with surrounding gate structure Dual material achieve a foremost responsibility to mitigate the device shrinking effects, impel to raise the ION current (10−3A/μm) and diminish the leakage current IOFF of 10−18A/μm to boost the ION/IOFF ratio as 1015. To guarantee the scalability and responsiveness of the device simulations has been done with Synopsys TCAD simulator tool.

TCAD-моделирование нанометровых структур FinFET на объемном кремнии с уче-том воздействия радиации

Transition from planar MOSFET structures to FinFET 3D structures ensures various radiation type resistance. However, the characteristics of radiation-exposed devices made at different factories vary considerably and it is hard to explain FinFET structures’ radiation resistance dependence on variations of their physical and topological parameters and electrical modes. In this work, a RAD-TCAD model of FinFET on bulk silicon was developed. Additional semi-empirical radiation dependences specific to FinFET structures were introduced into the basic model of a nanometer MOSFET: the charge carrier effective mobility, the traps concentration in the SiO2 and HfO2 oxides and at the Si / SiO2 interface. The model was implemented in the Sen-taurus Synopsys TCAD environment. The model was validated on a test set of FinFET structures with a channel length from 60 nm to 7 nm before and after exposure to gamma irradiation in the dose range up to 1 Mrad. Comparison of the modeled and experimental I-V characteristics has shown an error of no more than 15 %.

Identification of Electrically Stressed Regions in AlGaN/GaN-on-Si Schottky Barrier Diode Using EBIC Technique

The mapping of the current induced by a focused electron beam in a scanning electron microscope (SEM) has been used to localize electrically stressed regions in the AlGaN/GaN-on-Si Schottky barrier diode (SBD) structures cross-sectioned by the focused ion beam (FIB) technique. We have shown that homogeneously distributed electron beam induced current (EBIC) intensity detected below the Schottky contact at 0 V changes with increasing reverse voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</sub> and peaks at the edges of a field-plate region. The build-up of local microavalanches at high electric voltages has been indicated by overexposed EBIC signal at areas following the edges of the field plate structure. Interpretation of EBIC measurements is supported by electro-physical modeling and simulations employing the 2-D finite element method in Synopsys TCAD Sentaurus. The simulations prove that the electric field intensity in the SBD locally reaches values sufficiently high to trigger multiplication of the excessive carriers generated by an electron beam, which helps one to visualize and localize critical regions in GaN-based power electronic devices by the EBIC method.

A fast avalanche Si diode with a 517 μ m low-doped region

A silicon-avalanche shaper/sharpener is a fast-closing semiconductor switch. For positive voltages, it is activated by a high-voltage pulse at its cathode, and, when turned on, the current through the device rises rapidly. Using Synopsys TCAD software, a p+−n−n+ diode is numerically studied. It was shown that for the case of a high-doped active n region, 1014 cm−3, the breakdown process exhibits a fast electric field propagation, as expected. For a low doped active n region, &amp;lt;1011 cm−3, the electric field spreads uniformly along the structure. For this case, we show that the rise time, of the order of 100 ps, is not limited by the active region thickness, allowing the use of a thicker substrate in order to increase the operating voltage. A p+−n−n+ diode was fabricated on a thick, 525 μm, float-zone n-type Si (100) substrate, with a resistivity of 104 Ω cm. The active region, n&amp;lt;1012 cm−3, was 517 μm. When a stack of five, 8 mm2, diodes was driven by an ∼100 kV, 2.26 ns rise time pulse, the output voltage was 46 kV with the rise time and rise rate per diode of 215 ps and 38.4 kV/ns, respectively. When a single, 4 mm2, diode was driven by a 14 kV, 1 ns rise time pulse, the output on a 50 Ω load was around 8 kV, 100 ps, with a rise rate of 57 kV/ns. These results exceed the present state-of-the-art diodes. Furthermore, the thick active region eliminates current fabrication process difficulties such as deep diffusion or thick epitaxial layers.

Simulation study of single event effects sensitivity on commercial power MOSFET with single heavy ion radiation

High-frequency semiconductor devices are key components for advanced power electronic system that require fast switching speed. Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the most famous electronic device that are used in much power electronic system. However, the application such as space borne, military and communication system needs Power MOSFET to withstand in radiation environments. This is very challenging for the engineer to develop a device that continuously operated without changing its electrical behavior due to radiation. Therefore, the main objective of this study is to investigate the Single Event Effect (SEE) sensitivity by using Heavy Ion Radiation on the commercial Power MOSFET. A simulation study using Sentaurus Synopsys TCAD software for process simulation and device simulation was done. The simulation results reveal that single heavy ion radiation has affected the device structure and fluctuate the I-V characteristic of commercial Power MOSFET.

Suppression of buried oxide induced variability on digital performance of GeOI pMOSFETs using substrate bias scheme

Random variation in buried oxide thickness strongly affects the digital performance of ultra-thin body germanium-on-insulator MOSFETs. Dependencies of threshold voltage, ON-current, OFF-current and subthreshold slope of ultra-thin body germanium-on-insulator MOSFETs on three different BOX dielectrics are examined by employing well-calibrated Synopsys TCAD. The variation of threshold voltage and ON-current becomes less sensitive with high-k BOX dielectrics whereas smaller variation of OFF-current is observed for the device with low-k BOX dielectrics. The subthreshold slope remains almost unaltered for all BOX dielectrics. Furthermore, a positive substrate bias is found to suppress variability of digital performance parameters of GeOI p-MOSFETs.

Impact of two gate oxide with no junction metal oxide semiconductor field effect transistor- an analytical model

Abstract An analytical model based on physics is used to describe the potential distribution, horizontal electric field, and drain current of Two Gate Oxide with no junction MOSFET (TOX-NOJ-MOSFET) was investigated for cylindrical shape structure. The Poisson equation is used to derive the expression for cylindrical coordinate system which relies on parabolic approximation method. The combination of high k two gate oxide stack and junctionless transistor with Dual material Double gate structure performs a major role to diminish the short channel effects, propelled to increase the ION current (10−5A/μm) and decrease the leakage current IOFF of 10−14 A/μm to enhance ION/IOFF ratio to 109. To ensure the scalability and responsiveness of the system numerical simulations have been performed with various bias voltages and gate length ratios using Synopsys TCAD software and the results were well matched with analytical solutions.

Investigation of a Ge-Source Vertical TFET With Delta-Doped Layer

In this article, a $\delta $ -doped germanium-source vertical TFET (Ge-source vTFET) is proposed and investigated by Synopsis TCAD simulation. Higher ON-state current is obtained as the electron tunneling takes place in a direction parallel to the gate electric field. The incorporation of the $\delta $ -doped layer in the germanium source region further reduces the OFF-state leakage current. The impact on the variation of the device geometric dimensions has been studied for various electrical parameters and the dimensions are optimized accordingly through extensive simulations. A very high current ratio of the order ~1011 with a substantially low average subthreshold swing of 21.2 mV/decade is achieved. Benchmarking of the proposed Ge-source vTFET with other novel TFETs is carried out which produced better results in terms of high ON -state current and SSavg. The results obtained for the proposed vTFET make it a potential candidate for ultralow-power applications.

Optimization of insulated HfO&lt;sub&gt;2&lt;/sub&gt; dielectrics of GaN/InN/GaN/ In&lt;sub&gt;0.1&lt;/sub&gt;Ga&lt;sub&gt;0.9&lt;/sub&gt;N enhancement mode of MIS-HEMT heterostructure for high frequency power amplifier applications

In this paper, the enhancement-mode operation of the hetestructure of GaN/InN/GaN/In 0.1 Ga 0.9 N of the Metal Insulator Semiconductor High Electron Mobility Transistor (MIS-HEMTs) device having lnN-channel was investigated. The effect of scaling the device dimensions of Metal Insulator, such as the dielectric thickness of HfO 2 and the channel lengths, on the electrical performances was analyzed and compared to the currently used heterostructure. The numerical simulation of synopsis TCAD used showed a significant improvement in the electrical properties of the device that achieved a threshold voltage (V T ) = 0.828 maximum drain current of 1.77 A/mm V, transconductance (g m ) of 2.29 S.mm −1 , lowest ON-state resistance (R ON ) of 0.21 Ω.mm, and along with high-frequency performance achieving f T / f max of 98 GHz/129 GHz and 200 GHz/ 360 GHz respectively. The simulations also showed that this scaled GaN/ InN/ GaN/ In 0.9 Al 0.1 N heterostructure MIS-HEMT is an excellent substitute to the currently used MIS-HEMTs for delivering high power density and frequency at RF/power amplifier applications. Keywords: Enhancement mode, Hydrodynamic simulation, InN channel, MIS-HEMT, In 0.9 Al 0.1 N barrier/buffer, HfO 2 , TCH, Transconductance

A Holistic Approach on Junctionless Dual Material Double Gate (DMDG) MOSFET with High k Gate Stack for Low Power Digital Applications

The 2D analytical models for electrostatic potential, threshold voltage, subthreshold swing, Drain Induced Barrier Lowering (DIBL) and drain current of the Dual Material Double Gate junctionless transistor with high k gate structure is revealed. The electric field is obtained by solving Poisson equation with the help of parabolic approximation technique. The high k gate stack engineered (JL DMDG stack MOSFET) exaggerate the ION current of 10−4 (A/μm) and IOFF current of 10−14(A/μm) gives a remarkable amount of leakage current reduction. The short channel effects are quashed with the symmetric high k gate stack structure to a good extent. The device characteristics have been analyzed for various different high k materials. The significant outcomes of analytical solutions are mapped with the numerical solutions from Synopsys TCAD device simulator to affirm and validate the device structure. The JL DMDG Stack MOSFET based inverter circuit was also implemented to empower the device performance in digital applications. The voltage transfer characteristics, noise margin, delay and power dissipation of the JL DMDG stack MOSFET inverter circuit is assessed through numerical simulator with the help of Verilog-A language show substantial improvement due to this gate stack engineering model.

Design and Optimization of SiC Super-Junction MOSFET Using Vertical Variation Doping Profile

In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance ( ${R}_{\text {sp,on}}$ ). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge ( ${Q}_{g}$ ) and miller capacitance ( ${c}_{\text {rss}}$ ) compared to SJ MOSFET.

Temperature distribution on dielectric membrane structures for sensitive elements of semiconductor gas sensors

The aim of this article is to show a simulation of temperature distribution on dielectric membrane structures with membranes of different dielectric materials in the measuring mode of a semiconductor gas sensor. The simulation results were obtained using the software package Synopsys TCAD. In various moments of the measuring cycle were obtained two-dimensional temperature distributions on membrane structures. Dependencies of temperature versus time for the variety of the coordinates on membranes, temperature versus coordinates at the sensitive layer area’s highest heat value and temperature versus time in the center of the membranes are presented. Recommendations are given for the selection of membrane material for the heat-insulating membrane structure of sensitive elements for semiconductor gas sensors.

High Breakdown Voltage and Low On-Resistance 4H-SiC UMOSFET with Source-Trench Optimization

In this paper, a trench metal oxide semiconductor field-effect transistor (UMOSFET) with source oxide is proposed and studied by Synopsys TCAD software. The proposed structure has source trenches and optimized characteristics by changing parameters (source-trench depth, source oxide thickness, source Poly-Si thickness) constituting the source trench to improve device characteristics. As a result, source-trench depth, source Poly-Si thickness, and source oxide thickness were optimized to 2.4 μm, 2.3 μm, and 100 nm, respectively. Also, the proposed device has a higher breakdown voltage of 274 V compared to the conventional structure. In addition, the electric field is dispersed by the source-trench, and thus, the electric field applied to the gate oxide of the device is reduced to 0.7 MV/cm. This reduction improves the reliability of the device. The on-resistance was found to be reduced by 47% when a device with the same breakdown voltage was designed.

A Physical Model of an SOI Field-Effect Hall Sensor

Studies in the field of the development of new structures of Hall sensor with improved characteristics, in particular with increased magnetic sensitivity are in high demand. A physical model is proposed, which explains features of the Hall–hate characteristic and the formation of the increased magnetic sensitivity region in the SOI field-effect Hall sensor (SOI FEHS). The results of simulation in the Synopsys TCAD system confirm the proposed physical model of SOI FEHS functioning. The model explains features of the Hall–gate characteristic of the SOI FEHS in a wide range of gate voltages and allows the conclusion that the SOI FEHS has two operating regions and their choice is dictated by specific conditions of the sensor application. To achieve the maximum magnetic sensitivity, regions of partial depletion and enhancement should be chosen. To provide high noise immunity, it is reasonable to choose the full enhancement modes.

The Influence of the Dopant Concentration in a Silicon Film on the Magnetic Sensitivity of SOI Field-Effect Hall Sensors

SOI field-effect Hall sensors (SOI FEHS) are characterized by enhanced functionality but low magnetic sensitivity. The main task of the present study is to search for a way to increase the magnetic sensitivity of such sensors. The results of the study on magnetically sensitive electric characteristics of the SOI FEHSs, obtained using the process and device simulation system Synopsys TCAD, are presented. Three-dimensional device simulation is carried out. The calculated Hall-gate characteristics of the SOI FEHS are obtained, which confirm an earlier proposed sensor physical model according to which, under certain conditions of SOI FEHS operation, a region of increased magnetic sensitivity appears. The influence of the dopant concentration in the sensor channel on magnetic sensitivity is studied. It is shown that the magnetic sensitivity of SOI FEHS triples at a concentration of phosphorus in a working layer of NP = 1016 cm–3. The extended dynamic range of the region of increased magnetic sensitivity (wider than 5 V) permits us to broaden the area of the sensor’s practical application by increasing its noise immunity. The calculated SOI FEHS characteristics agree closely with the earlier published parameters of the experimental devices.