A Numerical Investigation of Stacked Oxide Junctionless High K with Vaccum Metal Oxide Semiconductor Field Effect Transistor

Abstract

The amalgamation of high dielectric permittivity material along with vaccum based dual material junctionless transistor with surrounding gate (DUM-HIK-VAC-JLSG-MOSFET) was investigated in this paper. The diverse oxide gate stack architecture of DUM-HIK-VAC-JLSG-MOSFET abate various effects arise due to channel shrinking. The evaluation of various parameters such as potential distribution in the channel region, electric field (transverse, lateral), transconductance, electron current density and drain current has been analyzed and a comparative statement between DUM-HIK-VAC-JLSG-MOSFET and the single material gate junctionless high k and vaccum double gate MOSFET(SIM-HIK-VAC-JLSG-MOSFET). The commingle of high dielectric permittivity material with vaccum as gate oxide stack and junctionless transistor with surrounding gate structure Dual material achieve a foremost responsibility to mitigate the device shrinking effects, impel to raise the ION current (10−3A/μm) and diminish the leakage current IOFF of 10−18A/μm to boost the ION/IOFF ratio as 1015. To guarantee the scalability and responsiveness of the device simulations has been done with Synopsys TCAD simulator tool.