Low-power Circuit Applications Research Articles

A physics based model for negative capacitance TFET considering variation in ferroelectric parameters

Here, an explicit analytical model of electrical properties like channel potential, electric field, drain current, and threshold voltage for a negative capacitance DGTFET structure is developed. The model properly calculates the channel potential profile by solving the Poisson equation using the Landau-Khalatnikov (LK) model (for incorporating the NC effect). The electric field expression is developed using a channel potential model. The drain current expression is obtained by mathematically integrating the rate of band-to-band tunneling generation over the channel thickness. The threshold voltage has been derived using a method called maximal trans-conductance. Furthermore, by varying the FE parameters like thickness (t fe ), coercive field (E C ), and residual polarization (P R ), we improve capacitance matching and gate control of the device. All of the model results demonstrated a perfect alignment with those discovered by TCAD simulations. Designing devices and circuits for low-power applications can be more effective from these results.

Projected performance of Si- and 2D-material-based SRAM circuits ranging from 16 nm to 1 nm technology nodes.

Researchers have been developing 2D materials (2DM) for electronics, which are widely considered a possible replacement for silicon in future technology. Two-dimensional transition metal dichalcogenides are the most promising among the different materials due to their electronic performance and relatively advanced development. Although field-effect transistors (FETs) based on 2D transition metal dichalcogenides have been found to outperform Si in ultrascaled devices, the comparison of 2DM-based and Si-based technologies at the circuit level is still missing. Here we compare 2DM- and Si FET-based static random-access memory (SRAM) circuits across various technology nodes from 16 nm to 1 nm and reveal that the 2DM-based SRAM exhibits superior performance in terms of stability, operating speed and energy efficiency when compared with Si SRAM. This study utilized technology computer-aided design to conduct device and circuit simulations, employing calibrated MoS2 nFETs and WSe2 pFETs. It incorporated layout design rules across various technology nodes to comprehensively analyse their SRAM functionality. The results show that, compared with three-dimensional structure Si transistors at 1 nm node, the planar 2DMFETs exhibited lower capacitance, leading to reduced cell read access time (-16%), reduced time to write (-72%) and lowered dynamic power (-60%). The study highlights the provisional benefits of using planar 2DM transistors to mitigate the performance degradation caused by reduced metal pitch and increased wire resistance in advanced nodes, potentially opening up exciting possibilities for high-performance and low-power circuit applications.

Solution-processed rare-earth thulium oxide with high permittivity for low-voltage transistor and inverters applications

The use of high-permittivity (high-k) thin films as gate dielectrics is essential in the development of low-power electronics. In this work, rare-earth thulium oxide (Tm2O3) thin films were prepared by a facile solution process and annealed at various temperatures from 400 to 700 °C. The evolution of the physical and dielectric properties of Tm2O3 thin film with annealing temperature was investigated. It is demonstrated that the Tm2O3 thin film annealed at 600 °C exhibits the optimal performance, including a low leakage current of 3 × 10−10 A/cm2, a large areal capacitance of 250 nF/cm2 at 100 Hz, and a high permittivity value of 14.2. The Tm2O3 thin film as a gate insulator was integrated into the thin film transistor (TFT) employing In2O3-based semiconducting channels. The In2O3 TFT with 600 °C-annealed Tm2O3 dielectric exhibits the superior performance, with a high Ion/Ioff of 1.65 × 107, a small subthreshold swing (SS) value of 0.2 V/dec, a VTH of +1.8 V, and a mobility of 1.68 cm2/(V·s). Furthermore, an inverter constructed by connecting the TFT with a resistor exhibits full-swing characteristics. This work provides a facile and appealing method for preparing the high-k Tm2O3 thin films as alternative gate dielectrics with the potential for use in low-power electronics and logic circuit applications.

A New Tunable Gyrator-C-Based Active Inductor Circuit for Low Power Applications

A new CMOS implementation of active inductor circuit based on the gyrator-C which is suitable for low-voltage and RF applications is presented in this paper. One of the critical features of active inductors which directly affect their quality factor is their series-loss resistance. In this regard, a multi-regulated cascade stage is employed in the new structure which decreases loss. Moreover, by cascading input transistor, the transistors which determine the self-resonance frequency and quality factor will be separated from each other. This results in arranging properties of designed active inductor independently. The configuration of two-stage conventional gyrators is improved which gives the proposed design more opportunities in determining and tuning its characteristics. Also by employing common-source configuration, low conductance nodes are achieved which decrease the ohm-loss of AI. Furthermore, main properties of design can be tuned without affecting each other. The power consumption of the circuit remains as low as 0.62[Formula: see text]mW, then the circuit is suitable for low power applications. The results showed that AI is suitable for RF applications over 0.2–11.8[Formula: see text]GHz frequency range. In order to verify theoretical calculations, simulations are carried out using HSPICE and level 49 parameters (BSIM3v3) in 130[Formula: see text]nm CMOS technology. In addition, Corner and Monte Carlo analyses are considered to prove the efficiency of the circuit against the process variation.

Buck-Boost Type High Step-Down Low Power Modular Converter for Medium Voltage DC Systems

The medium-voltage dc (MVDC) system are intensely investigated by both industry and academy. However, how to realize a lower power circuit directly fed by MVDC is an important but easily neglected problem, which seriously affects the reliability of the dc system. The current high step-down circuits are mostly suitable for high-power applications, while the circuits for low-power applications are designed case by case. To address the obstacle, a generalized buck-boost type high step-down converter (BHSC) structure is proposed in this article. The submodules of BHSC are derived from basic dc–dc converter. As a result, the features of high modularity, simple structure, and low cost can be obtained, and each submodule operates independently without communication and synchronization to achieve voltage balance. Furthermore, a submodule strategy with Bang-Bang control, instead of hardware modification, is proposed to overcome the limitation of BHSC generality in medium-voltage (MV) and high-voltage (HV) applications, due to the operating current difference in different submodules of the cascaded structure. Therefore, BHSC can be easily extended to MV or HV by increasing the number of submodules. Finally, an experimental evaluation of a 1 kV/80 W prototype converter is presented, which can be applied as auxiliary power supply for high-power converter.

A Soft Switched Single Ended Primary Inductor Converter Power Factor Correction Circuit for Low Power Applications

Wydawnictwo SIGMA-NOT wydaje czasopisma fachowe informujące swoich czytelników o najnowszych osiągnięciach naukowych i nowoczesnych rozwiązaniach technicznych w Polsce i na świecie, popularyzuje problemy techniczne oraz poszerza wiedzę i kulturę techniczną.

Comprehensive Study of Inversion and Junctionless Ge Nanowire Ferroelectric HfZrO Gate-All-Around FETs Featuring Steep Subthreshold Slope with Transient Negative Capacitance

This study reports the ferroelectric (FE) layer of Hf0.5Zr0.5O2 (HZO) film on a Ge gate-all-around field-effect-transistor (GAAFET) with inversion mode (IM) and junctionless (JL) mode, and is the first that discuss the association of the JL field-effect transistor conduction mechanism in the subthreshold region with the transient negative capacitance (TNC) effect of the FE layer are discussed. The IM Ge FE-GAAFET exhibited a minimum subthreshold slope (SSmin) of 55 mV dec−1 and a high ION/IOFF ratio of >106. The sub-60 mV dec−1 SS result demonstrates surface potential amplification, which is attributed to the TNC effect. Furthermore, the Ge JL FE-GAAFETs exhibited an SSmin of 58 mV dec−1, a high ION/IOFF ratio (>105), and reverse drain-induced barrier lowering when compared with baseline HfO2 devices. These IM and JL Ge FE-GAAFETs are highly suitable for low-power integrated circuit applications.

Temperature-Dependent Analytical Modeling of Graded-Channel Gate-All-Around (GC-GAA) Junctionless Field-Effect Transistors (JLFETs)

In this paper, analytical modeling of center channel potential has been performed for graded-channel gate-all-around (GC-GAA) junctionless field-effect transistor (JLFET). The three-dimensional (3D) Poisson’s equation has been solved to discover the center channel potential utilizing the parabolic approximation equation with excellent boundary conditions. The minimum center channel potential has been adopted to calculate the subthreshold current by the drift-diffusion method. The effect of high temperature and doping concentration on the center potential and subthreshold current has been investigated, and the results have been verified. The validity of the model has been verified using the ATLAS TCAD device simulator. The results reveal that the GC-GAA JLFET reduces the OFF-state leakage current with a high-graded abrupt junction inside the channel region. Hence, this finds many applications in low-power, high-speed, and high-density circuits.

Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications

Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the charge pump topologies based on input/output voltage, pumping efficiency, power dissipation, charge transfer capability, design complexity, pumping capacitor, clock frequencies with a minimum load balance, etc. Finally, this review study summarizes with the discussion on the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications.

Unified compact model for junctionless multiple-gate FETs including source/drain extension regions

This paper presents a unified compact model for a junctionless (JL) multiple-gate (MG) FET operating in the subthreshold region. A unified center potential model for double-gate, triple-gate, and quadruple-gate (QG) JL FETs is obtained using a quasi-3D scaling equation. The source/drain (S/D) extension regions are also modeled depending on the S/D extension length. The subthreshold current and subthreshold characteristics such as the subthreshold slope, threshold voltage, and drain-induced barrier lowering are analytically modeled for JL MG FETs. Comparison of the proposed models with numerical simulation results obtained using Sentaurus TCAD showed good accuracy, even for a very-short-channel QG device with a channel length of 10 nm. The proposed compact model can be used for low power circuit applications of JL MG FETs.

Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications

In this paper, a new technique ONOFIC is proposed and implemented for designing the SiGe heterojunction 2D double gate Vertical t-shaped TFET as an inverter circuit for low power applications. Initially, simulation done for both P-type and N-type of Vertical tTFET with same attributes using Sentaurus TCAD simulation tool. Thereafter, mixed mode technique is employed to understand the inverter circuit simulation’s electrical characteristics and circuit efficiency. The workfucntion used for n-type Vertical TFET is 4.5 eV and for p-type Vertical TFET is 5.6 eV respectively. A 2D analytical model also implemented to capture the affecting parameters of leakage current and depletion length of the proposed model. Moreover, a new block technique named ONOFIC is inserted between the pull-up network and pull-down network of the circuit to regulator the trade-off between the power dissipation and reduced device dimensions. The method offers an excellent agreement between the propagation delay and power dissipation for designing efficient logic circuit. This article compares the efficiency of logic circuit like NAND, NOR and inverter circuit by estimating the power-delay product (PDP) with the conventional logic designs. The performance result show that the proposed model significantly reduces the leakage current for low power circuit applications.

Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance

Abstract In this work, an innovative structure of a novel double gate tunnel field-effect transistor (TFET) is proposed with a channel length of 20 nm.The gate dielectric regions have been renovated by inserting metal strips and using stacked gate-oxide concept. The device exhibits suppressed ambipolar current, excellent subthreshold swing and good ION/IOFF ratio. The proposed structure proves to be a promising candidate for high speed applications as it shows lesser gate-capacitance than conventional stacked-oxide gate structure. The surface potential and electric field have been modelled considering the depletion regions, using 2-D Poisson's equation with appropriate boundary conditions, based on parabolic potential approximation. A semi-empirical method has been utilized to incorporate the effect of mobile charges on the device characteristics. A physics-based model for charge and terminal capacitances has been derived, following the potential model. The drain current model is able to accurately predict the ambipolar current as well as the effects of drain voltage in saturation region. Proper optimization of the device structure has been performed to derive the best desired electrical characteristics. SILVACO ATLAS simulation data have been used to validate the analytical results of the proposed structure, thereby corroborating the precision of the present analytical model. Finally, an inverter circuit has been designed in CADENCE circuit-simulation environment to justify the usage of our device in low power and high speed digital circuit applications.

High-performance lateral MoS2-MoO3 heterojunction phototransistor enabled by in-situ chemical-oxidation

Construction of in-plane p-n junction with clear interface by using homogenous materials is an important issue in two-dimensional transistors, which have great potential in the applications of next-generation integrated circuit and optoelectronic devices. Hence, a controlled and facile method to achieve p-n interface is desired. Molybdenum sulfide (MoS2) has shown promising potential as an atomic-layer n-type semiconductor in electronics and optoelectronics. Here, we developed a facile and reliable approach to in-situ transform n-type MoS2 into p-type MoO3 to form lateral p-n junction via a KI/I2 solution-based chemical oxidization process. The lateral MoS2/MoO3 p-n junction exhibits a highly efficient photoresponse and ideal rectifying behavior, with a maximum external quantum efficiency of ∼650%, ∼3.6 mA W−1 at 0 V, and a light switching ratio of ∼102. The importance of the built in p-n junction with such a high performance is further confirmed by high resolution photo current mapping. Due to the high photoresponse at low source-drain voltage (VDS) and gate voltage (VG), the formed MoS2/MoO3 junction p-n diode shows potential applications in low-power operating photodevices and logic circuits. Our findings highlight the prospects of the local transformation of carrier type for high-performance MoS2-based electronics, optoelectronics and CMOS logic circuits.

Assessment of On-Chip Current Sensor for Detection of Thermal-Neutron-Induced Transients

This article assesses, for the first time, a body/bulk built-in current sensor (BBICS) in a CMOS 65-nm test chip under thermal neutron, high-energy neutron, and laser radiation. Experimental results suggest that the on-chip current sensor is effective to detect transient faults in different case-study subcircuits of the chip exposed to the accelerated radiation effects, opening prospects for embedding this type of sensor in reliable, secure, and low-power integrated circuit applications.

Two-dimensional modeling of the underlap graded-channel FinFET

The graded n-channel underlap fin-shaped field-effect transistor (FinFET) provides ample scope for future investigation. This device and the effects of the underlap, gate length, and doping concentration of the short channel are analyzed herein using two-dimensional (2-D) modeling. The proposed structure includes four regions, in each of which a potential function is developed by applying boundary conditions on Poisson’s equation. The parabolic potential profiles in the graded channel region and the underlap regions are found to depend on the bias at the gate/drain terminals, the doping profile, the channel length, and the underlap length, ensuring the reliability of the device for low-power circuit applications. The results of this analysis are validated against numerical solutions obtained using a 2-D device simulator, revealing an exact match.

An efficient Verilog-A memristor model implementation: simulation and application

Complementary metal–oxide–semiconductor (CMOS) technology is reaching its limits due to the continuous shrinking process, which has an impact on various aspects including device size, performance, and power consumption. The memristor is one of the promising devices under investigation for use with deep-nanometer CMOS, having applicability in several fields due to its nonlinear behavior, nonvolatility, low power consumption, high density, and CMOS compatibility. Several models for memristors have been developed to date, but there is a requirement for compact models that are both flexible and sufficiently accurate. A general memristor model generated in Verilog-A is discussed herein to confirm its behavior in the one-transistor one-resistor (1T1R) oxide-based random-access memory (OxRAM) configuration, and validated at circuit level. The results of the model correlate well with experimental characterization data for the HfO2-based OxRAM memristor device, describing the characteristics of both its bipolar and unipolar memristor behaviors. The 1T1R structure is analyzed using the Spectre circuit simulator. Two cases are considered, using the cell as either programmable read-only memory (PROM) or electrically erasable programmable read-only memory (EEPROM). The simulation results confirm the desired nonlinear memristor characteristic, and the applicability of the model to fit and simulate different switching behaviors. The results are verified against both electrical and experimental characterization data, suggesting that the Verilog-A model is suitable for low-power and high-density logic circuit applications at the industrial level.

0.5 V bulk ‐ driven CMOS fully differential current feedback operational amplifier

This study presents a new low-voltage fully differential current feedback operational amplifier for ultra-low-voltage and low-power analogue circuit applications. A bulk-driven technique is used to reduce the supply voltage requirement and also provides a rail-to-rail input voltage common-mode swing. The proposed circuit has been simulated using a TSMC 0.18 µm n-well CMOS technology with a 0.5 V supply voltage. Simulation results show that the static power consumption of the proposed circuit is 4.7 µW. The proposed circuit has been used to realise fully differential integrators and fully low-pass/band-pass second-order filters to express the performance of the new circuit.

Estimation of Power for Reversible Subtractors

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG). Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor. Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.

Metal–Insulator–Graphene Diode Mixer Based on CVD Graphene-on-Glass

In this letter, we present for the first time a mixer circuit based on Metal–Insulator–Graphene (MIG) diodes fabricated with large-scale monolayer graphene grown by chemical vapor deposition. A small-signal model extracted from the diode physical structure is used together with a large-signal model extracted from the dc characteristics of the MIG diode to build a down-conversion mixer. The measured conversion loss at a local oscillator power ( ${P}_{\text {LO}}$ ) of 5 dBm is lower than 15 dB, while RF-to-IF isolation is 36 dB with an input return loss and RF-to-LO isolation better than 10 dB over the frequency band from 1.7–6 GHz. Promising mixer results in combination with the CVD-based process promote the MIG diode-based mixer to be used in low-power, low-cost, microwave, and millimeter-wave circuit applications.

Analysis of GaN nanoscale FinFET for low power circuit applications

This work introduces a structure of GaN FinFET at the nanoscale (channel length L = 5 nm) and characterises its performance in low power circuit applications. The simulated outcomes justify its application in circuits having I ON , I OFF , and I ON / I OFF of the order of ∼ 10 − 3 A , ∼ 10 − 13 A , and ∼ 10 10 A , respectively, with quality factor Q = 1.11 × 10−5 S-dec/mV computed at I OFF ∼ 10 − 13 A and V DS = 0.5 V. The measured observations are compared with other materials and we observed significant improvement, of the orders of 1 in the case of I ON and 3 in the case of I OFF ; while the same for the Q witnesses a growth of 42%, especially with respect to silicon. The prospect of the proposed device architecture has also been investigated by implementing it in the digital circuits such as the inverter and universal logic gates (NAND and NOR gates), where it showed improved performance like high gain and absence of overshoot and undershoot in the switching characteristics.