Unified compact model for junctionless multiple-gate FETs including source/drain extension regions

Abstract

This paper presents a unified compact model for a junctionless (JL) multiple-gate (MG) FET operating in the subthreshold region. A unified center potential model for double-gate, triple-gate, and quadruple-gate (QG) JL FETs is obtained using a quasi-3D scaling equation. The source/drain (S/D) extension regions are also modeled depending on the S/D extension length. The subthreshold current and subthreshold characteristics such as the subthreshold slope, threshold voltage, and drain-induced barrier lowering are analytically modeled for JL MG FETs. Comparison of the proposed models with numerical simulation results obtained using Sentaurus TCAD showed good accuracy, even for a very-short-channel QG device with a channel length of 10 nm. The proposed compact model can be used for low power circuit applications of JL MG FETs.