Low-power Circuit Applications Research Articles

On the Temperature-Dependent Electron Impact Ionizations in a Step-Graded InAlGaAs∕InP Collector Double Heterojunction Bipolar Transistor

The temperature-dependent electron impact ionizations of an InP/InGaAs double heterojunction bipolar transistor (DHBT) with a step-graded InAlGaAs/InP collector structure are studied and demonstrated from 300 to 400 K. Experimentally, the multiplication factor and electron ionization coefficient are increased with increasing temperature. Furthermore, the studied device shows a lower multiplication factor and weaker temperature dependence as compared with conventional InP/InGaAs HBTs. Therefore, the studied DHBT device with a step-graded InAlGaAs/InP collector structure provides promise for low-voltage and low-power circuit applications.

A novel InGaP/Al/sub x/Ga/sub 1-x/As/GaAs CEHBT

A new and interesting InGaP/Al/sub x/Ga/sub 1-x/As/GaAs composite-emitter heterojunction bipolar transistor (CEHBT) is fabricated and studied. Based on the insertion of a compositionally linear graded Al/sub x/Ga/sub 1-x/As layer, a near-continuous conduction band structure between the InGaP emitter and the GaAs base is developed. Simulation results reveal that a potential spike at the emitter/base heterointerface is completely eliminated. Experimental results show that the CEHBT exhibits good dc performances with dc current gain of 280 and greater than unity at collector current densities of J/sub C/=21kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 2.70×10/sup -5/ A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. A small collector/emitter offset voltage /spl Delta/V/sub CE/ of 80 meV is also obtained. The studied CEHBT exhibits transistor action under an extremely low collector current density (2.7×10/sup -5/ A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and useful current gains over nine decades of magnitude of collector current density. In microwave characteristics, the unity current gain cutoff frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> =43.2GHz and the maximum oscillation frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> =35.1GHz are achieved for a 3×20 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> device. Consequently, the studied device shows promise for low supply voltage and low-power circuit applications.

MOS CURRENT MODE LOGIC CIRCUITS: DESIGN CONSIDERATION IN HIGH-SPEED LOW-POWER APPLICATIONS AND ITS FUTURE TREND, A TUTORIAL

In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.

DC Characterization of InP/InGaAs Tunneling Emitter Bipolar Transistor

An InP/InGaAs tunneling emitter bipolar transistor (TEBT) is studied and demonstrated. From the simulation results, the band diagram, tunneling transmission, and carrier distribution of the device are analyzed as functions of barrier thickness. The higher the emitter injection efficiency, the higher the current gain and the larger the current drivability for the device studied by employing a tunneling barrier layer of suitable thickness. In addition, experimentally, InP/InGaAs TEBT has been fabricated successfully. Due to its excellent tunneling barrier structure, the studied device can be operated under an extremely wide collector current range. The operation range is larger than 11 decades of collector current (10-12 to 10-1 A). Moreover, the studied device exhibits a very small collector-emitter offset voltage (ΔVCE) of 40 mV and an extremely wide operation range of output current. Thus, the studied device is suitable for low-voltage and low-power circuit applications.

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a mid-gap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P+/N+ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET.

Effect of substrate biasing on Si/SiGe heterostructure MOSFETs for low-power circuit applications

We have investigated the effect of substrate biasing on the subthreshold characteristics and noise levels of Si/Si/sub 1-x/Ge/sub x/ (x=0,0.15,0.3) heterostructure MOSFETs. A detailed analysis of the dependence of threshold voltage, off-state current, and low-frequency noise level on the substrate-source (V/sub bs/) biasing showed that SiGe heterostructure MOSFETs offer a significant speed advantage, an extended subthreshold operation region, a reduced noise level, and reduced bulk potential sensitivity compared to Si bulk devices. These experimental results demonstrate that SiGe heterostructure MOSFETs render a promising extension to the CMOS technologies at the low-power limit of operation, eventually making the micropower implementation of radio frequency (RF) functions feasible.

A novel InP/InGaAs TEBT for ultralow current operations

A novel InP/InGaAs tunneling emitter bipolar transistor (TEBT) is fabricated and demonstrated. The studied device exhibits a very small collector-emitter offset voltage of 40 mV and an extremely wide operation regime. The operation region is larger than 11 decades in magnitude of collector current (10/sup -12/ to 10/sup -1/A). A current gain of 3 is obtained even if the device is operated at an ultralow collector current of 3.9 /spl times/ 10/sup -12/A (1.56 /spl times/ 10/sup -7/A/cm/sup 2/). Furthermore, the common-emitter breakdown voltage of the studied device is higher than 2 V. Consequently, the studied device shows a promise for low supply voltage, and low-power consumption circuit applications.

High performance Si/SiGe heterostructure MOSFETs for low power analog circuit applications

We have demonstrated a high performance Si 1− x Ge x pMOSFET technology for low power circuit applications. The incorporation of 30% Ge in the strained Si 1− x Ge x channel provides a drive current enhancement by a factor of 2.7 over its counterpart Si bulk pMOSFETs and manifests a marked advantage of two decade in exponential operating region allowing both lower power consumption and a wider dynamic range for low power circuit applications. The measured low frequency noise in Si 1− x Ge x pMOSFET’s is found to be significantly lower than in Si devices. The experimental results promise the potential of SiGe/Si heterostructure MOSFETs in radio-frequency low power circuit applications.

Analysis of Si/SiGe channel pMOSFETs for deep-submicron scaling

Short-channel effects of Si 1− x Ge x p-channel MOSFETs have been examined by two-dimensional computer simulation. It is found that devices incorporating SiGe channel offer worthwhile advantages in device performance and scalability. In addition to enhanced drive current due to higher hole mobility, Si 1− x Ge x p-channel MOSFETs also provide better carrier confinement in the Si/SiGe quantum well, which leads to lower gate-controlled depletion charge and electric field in the subsurface. These in turn suppress the drain-induced barrier lowering and punch through effects in SiGe pMOSFETs compared to the bulk Si devices at the same physical dimension. Higher device performance and better scalability make Si 1− x Ge x p-channel MOSFETs a great benefit for high-speed and low-power CMOS circuit applications.

High-speed small-scale InGaP/GaAs HBT technology and its application to integrated circuits

We have developed the advanced performance, small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) by using WSi/Ti base electrode and buried SiO/sub 2/ in the extrinsic collector. The base-collector capacitance C/sub BC/ was further reduced to improve high-frequency performance. Improving the uniformity of the buried SiO/sub 2/, reducing the area of the base electrode, and optimizing the width of the base-contact enabled us to reduce the parasitic capacitance in the buried SiO/sub 2/ region by 50% compared to our previous devices. The cutoff frequency f/sub T/ of 156 GHz and the maximum oscillation frequency f/sub max/ of 255 GHz were obtained at a collector current I/sub C/ of 3.5 mA for the HBT with an emitter size S/sub E/ of 0.5/spl times/4.5 /spl mu/m/sup 2/, and f/sub T/ of 114 GHz and f/sub max/ of 230 GHz were obtained at I/sub C/ of 0.9 mA for the HBT with S/sub E/ of 0.25/spl times/1.5 /spl mu/m/sup 2/. We have also fabricated digital and analog circuits using these HBTs. A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB/spl middot//spl Omega/ with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed, low-power circuit applications.

Novel HEMT processing technologies and their circuit applications

The monolithic integration of enhancement- and depletion-mode high-electron mobility transistors (E- and D-HEMTs) suitable for high-speed and low power circuit applications in the lattice-matched InP material system is examined. E-HEMT devices with gate-lengths of 0.25, 0.5 and 1.0 μm fabricated using a buried-Pt gate process demonstrate threshold voltages ( V T) ranging from +200 to +258 mV and maximum extrinsic transconductances ( g mext) as high as 800 mS mm −1, while D-HEMT devices of identical gate-lengths exhibited a V T ranging from −599 to −405 mV, and a g mext as high as 578 mS mm −1. The devices showed excellent rf characteristics, exhibiting unity current-gain cutoff frequencies ( f t) as high as 106 GHz. Based on these results, 11, 23, and 59 stage ring oscillators using direct-coupled FET logic (DCFL) technology were fabricated and characterized. Room temperature propagation delays of 9.27 ps/stage with a power-delay product of 2.37 fJ/stage were achieved.

Design and analysis of high performance current reference generators for low-power CMOS data converters

Based on a highly accurate current divider using switched current technique without the need of well-matched components, a current reference generator (CRG) circuit is developed to generate and hold the weighed currents used in the data converters. This paper also presents a methodology for designing high-performance CMOS CRG circuits for low-power applications and their performance analysis for estimating the accuracy, speed, and power consumption. To demonstrate the design procedure and performance analysis, several design examples are given. The simulation results show that, for a 6-bit CRG circuit, its calibration time and holding time are 27 and 242 /spl mu/s, respectively, and for a 8-bit CRG circuit, they are 48 and 236 /spl mu/s, respectively. The circuit consumes 1.8 mW and achieves better than 10-bit accuracy, where a MOSIS SCNA20 2-/spl mu/m process and a 3.3-V supply voltage are employed. Thus, the developed CRG circuit is well suited for low-power/low-voltage and moderate resolution data converters.

Small-scaled InGaP/GaAs HBTs with WSi/Ti base electrode and buried SiO/sub 2/

This paper describes the fabrication and characteristics of small-scaled InGaP/GaAs HBTs with high-speed as well as low-current operation. To reduce both the emitter size S/sub E/ and the base-collector capacitance C/sub BC/ simultaneously, the HBTs are fabricated by using WSi/Ti as the base electrode and by burying SiO/sub 2/ in the extrinsic base-collector region under the base electrode. WSi/Ti simplifies and facilitates processing to fabricate a small base electrode, and makes it possible to reduce the width of the base contact to less than 0.4 /spl mu/m without the large increase in the base resistance. The DC current gain of 20 is obtained for an HBT with S/sub E/ of 0.3/spl times/1.6 /spl mu/m/sup 2/ due to the suppression of emitter size effect by using InGaP as the emitter material. An HBT with SE of 0.6/spl times/4.6 /spl mu/m/sup 2/ exhibited f/sub T/ of 138 GHz and f/sub max/ of 275 GHz at I/sub C/ of 4 mA; and an HBT with SE of 0.3/spl times/1.6 /spl mu/m/sup 2/ exhibited f/sub T/ of 96 GHz and f/sub max/ of 197 GHz at I/sub C/ of 1 mA. These results indicate the great potential of these HBTs for high-speed and low-power circuit applications.

High-speed InGaP/GaAs heterojunction bipolar transistors with buried SiO2 using WSi as the base electrode

High-speed InGaP/GaAs heterojunction bipolar transistors (HBT's) with a small emitter area are described. WSi is used as the base electrode to fabricate HBT's with a narrow base contact width and a buried SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> structure. An HBT with an emitter area of 0.8×5 μm exhibited an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 105 GHz and an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 120 GHz. These high values are obtained due to the reduction of C/sub BC/ by using buried SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> with a narrow base contact width, indicating the great potential of GaAs HBT's for high-speed and low-power circuit applications.

Low-current operation of high-speed InP/InGaAs heterojunction bipolar transistors

High-speed performance, f T > 100 GHz, at sub-milliampere collector currents is demonstrated with a laterally scaled-down InP/InGaAs heterojunction bipolar transistor (HBT) fabricated by using a combination of dry and wet etching techniques. This result indicates that small-sized InP/InGaAs HBTs are promising for low-power high-speed circuit applications. To cope with the characteristic problems of the small-sized devices, i.e. degraded current gain and increased base resistance, the influence of graded-base structure and emitter geometry on transistor performance is investigated with the result that the graded-base structure is effective for enhancing current gain, and that narrowing the emitter stripe width is effective for suppressing the increase in base resistance.

High-speed carbon-doped-base InP/InGaAs heterojunction bipolar transistors grown by MOCVD

State of the art fT and fmax values of 135 and 113 GHz for MOCVD grown C-doped base InP/InGaAs HBTs are achieved with a 0.5 × 4.7 µm2 emitter area device. A rapid increase in fT at a very low VCE value of 0.3 V owing to the abrupt base dopant profile demonstrates the suitability of C-doped-base HBTs for high-speed and low-power circuit applications.

Two-dimensional metal-semiconductor field effect transistor for ultra low power circuit applications

We describe a novel 2-dimensional metal-semiconductor field effect transistor (2-D MESFET) in which opposing Schottky side gates formed on the sidewall of a modulation-doped AlGaAs-InGaAs heterostructure modulate the channel width and the drain current. The drain current ranged from 0 to 210 μA and the maximum measured transconductance was 212 μS (212 mS/mm) at room temperature for a 1×1 micron channel. The threshold voltage was -0.45 V and the subthreshold ideality factor was 1.30. The estimated gate capacitance was 0.8 fF/μm, or about half the equivalent capacitance of conventional HFET's. The cutoff frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> was estimated to be 21 GHz. The narrow channel effect, which limits the minimum power consumption in conventional FET's, is practically eliminated in this device.

Recent Progress in SOI Materials and Devices for VLSI Applications

Silicon-On-Insulator (SOI) technology [1-4] has been shown to have significant performance and fabrication advantages over conventional bulk processing for a wide variety of large scale CMOS IC applications. Advantages in radiation environments has generated significant interest in this technology from military and space science communities [5,6]. Possible advantages of SOI technology for low power, low voltage and high performance circuit applications is under serious consideration by several commercial IC manufacturers [7,8].

A study of the frictional, wear and contact resistance performance of tin alloy coatings

The purpose of the present experimental study is to give an assessment of the extent to which tin alloy coatings are suitable as connector contact finishes in low power circuit applications. SnPb and SnNi alloy coatings were electrodeposited onto tin bronze and partially exposed to a thermal post-treatment. The performance of SnPb-coated contacts during mutual sliding is characterized by significant decreases in the frictional force and in its range of variation and, simultaneously, by an increase in the contact resistance by several orders of magnitude after a certain number of sliding cycles. Similar results were obtained for SnNi coatings. Investigations of the properties and structure of the coatings have clarified both the influence of heat treatment and the changes in frictional and contact resistance performance during sliding stress. For SnPb coatings a partial phase transition to metastable α-Sn due to mechanical stress was shown to occur along the wear tracks.