Analysis of GaN nanoscale FinFET for low power circuit applications

Abstract

This work introduces a structure of GaN FinFET at the nanoscale (channel length L = 5 nm) and characterises its performance in low power circuit applications. The simulated outcomes justify its application in circuits having I ON , I OFF , and I ON / I OFF of the order of ∼ 10 − 3 A , ∼ 10 − 13 A , and ∼ 10 10 A , respectively, with quality factor Q = 1.11 × 10−5 S-dec/mV computed at I OFF ∼ 10 − 13 A and V DS = 0.5 V. The measured observations are compared with other materials and we observed significant improvement, of the orders of 1 in the case of I ON and 3 in the case of I OFF ; while the same for the Q witnesses a growth of 42%, especially with respect to silicon. The prospect of the proposed device architecture has also been investigated by implementing it in the digital circuits such as the inverter and universal logic gates (NAND and NOR gates), where it showed improved performance like high gain and absence of overshoot and undershoot in the switching characteristics.