Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications

Abstract

In this paper, a new technique ONOFIC is proposed and implemented for designing the SiGe heterojunction 2D double gate Vertical t-shaped TFET as an inverter circuit for low power applications. Initially, simulation done for both P-type and N-type of Vertical tTFET with same attributes using Sentaurus TCAD simulation tool. Thereafter, mixed mode technique is employed to understand the inverter circuit simulation’s electrical characteristics and circuit efficiency. The workfucntion used for n-type Vertical TFET is 4.5 eV and for p-type Vertical TFET is 5.6 eV respectively. A 2D analytical model also implemented to capture the affecting parameters of leakage current and depletion length of the proposed model. Moreover, a new block technique named ONOFIC is inserted between the pull-up network and pull-down network of the circuit to regulator the trade-off between the power dissipation and reduced device dimensions. The method offers an excellent agreement between the propagation delay and power dissipation for designing efficient logic circuit. This article compares the efficiency of logic circuit like NAND, NOR and inverter circuit by estimating the power-delay product (PDP) with the conventional logic designs. The performance result show that the proposed model significantly reduces the leakage current for low power circuit applications.